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Using Multiple ZYNQ devices on the same board

Former Member

Hi all,

I am thinking of using multiple zynq soc on a single
board for embedded aerospace application.

with one device as front end processor, and while three other processor connected to the front end processor  that data shared from front end processor to the other processors are not huge while the data should be shared very quickly with minimal delay.  Can you please suggest any ideal interface for this.  If am using PCI express for this what is the configuration scheme required  ?

If the processor used for front end is configured as RC (complex) and others as end point (EP) , PCI express switch will be required .

As this forum is more on the discussions wrt ZED/micro ZED board details, I  just took a chance of posting this query. Any pointers highly appreciated.
regards
Chandra

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    For chip-to-chip connections in your application you have a few options:

    1)tAs you mentioned, you could use the PCIe interconnect with the front-end processor to be the Root-Complex (RC) and the other 3 processors as PCIe Endpoint devices. Since you are connecting the PCIe RC to multiple PCIe Endpoint devices, you would need to use a PCIe switch external to the front-end processor. In February we will be posting a PCIe RC reference design for the Avnet Mini-ITX board on ZedBoard.org, you could use this design as starting point. There is only one PCIe slot on the Avnet Mini-ITX board, so no external PCIe switch is used on this board. You would need to add a switch to adapt/port this reference design to your application.
    Since your application requires minimum delay/latency, you need to be aware of typical delays associated with the PCIe protocol. I would suggest you do some research in this area and make sure your application can handle the delays/latency associated with the PCIe protocol.

    2)tIn addition to the PCIe interconnect; you could use other simpler protocols such as Aurora or custom protocol. These interconnects are not one-to-many, so you would have to use multiple instances of the interface for devices connected to the front-end processor.