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"Zedboard HDMI display controller tutorial" has error on Vivado 2014.1

Former Member

I tried it a "Zedboard HDMI Display Controller Tutorial for Vivado" using vivado 2014.1, the following error has occurred.

Please tell me the workaround.

"[BD 41-1343] Reset pin / zed_hdmi_display/v_tc_0/resetn (associated clock / zed_hdmi_display/v_tc_0/clk)
is connected to reset source / zed_hdmi_display / proc_sys_reset / peripheral_aresetn
u00A0 (synchronous to clock source / processing_system7_0/FCLK_CLK1).

This may prevent design from meeting timing.
Please add proc_sys_reset module to create a reset, that is synchronous to
the associated clock source / clk_wiz_0/clk_out1. "

  • 0

    When I implemented this tutorial in Vivado 2013.3 it did implement the proc_sys_reset module that the error message is asking you to add. You might try working through the tutorial in 2013.3 first to validate your setup and see the implementation before trying to port to 2014.1. If the proc_sys_reset module does not get generated in 2014.1 I would suggest adding it manually in the same manner it is in the 2013.3 version.

     

    There are often small issues you need to deal with when moving designs to a new version of the tools.

     

    -Gary

  • 0

    my workaround is follows

    1. disconnect resetn of v_tc_0
    2. add new Processor System Reset (proc_sys_teset_0) IP
    3. connect slowest_system_clk pin of proc_sys_teset_0 to hdmil_clk
    4. connect ext_reset_in pin of proc_sys_teset_0 to axi4s_resetn
    5. connect perifheral_aresetn[0:0] pin to resetn of v_tc_0