Hi, I am just getting started so I began with the FMC-IMAGEON HDMI Display Controller Tutorial. I am at the bitstream generation step but I am having the following errors:
launch_runs impl_1 -to_step write_bitstream
[Ipptcl 7-5] XIT evaluation error: File writer encountered an error: c:/Xilinx/Vivado/2013.4/examples/Vivado_Tutorial/Projects/tutorial/tutorial.srcs/sources_1/bd/tutorial/ip/tutorial_axis_subset_converter_0_0/axis_subset_converter_v1_1/hdl/verilog/axis_subset_converter_v1_1_axis_subset_converter_tutorial_axis_subset_converter_0_0.v
[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2013.4/data/ip/xilinx/axis_subset_converter_v1_1/ttcl/axis_subset_converter_v1_1_axis_subset_converter_v.xit': ERROR: [Common 17-39] 'xit::puts_ipfile' failed due to earlier errors.
[IP_Flow 19-911] XIT detected an open writer channel for file 'c:/Xilinx/Vivado/2013.4/examples/Vivado_Tutorial/Projects/tutorial/tutorial.srcs/sources_1/bd/tutorial/ip/tutorial_axis_subset_converter_0_0/axis_subset_converter_v1_1/hdl/verilog/axis_subset_converter_v1_1_axis_subset_converter_tutorial_axis_subset_converter_0_0.v'. Please use 'close_ipfile' command to close channels before exit.
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-98] Generation of the IP CORE failed.
[BD 41-1030] Generation failed for the IP Integrator block /axis_subset_converter_0
Help on how to fix this is highly appreciated.
