Hi,
I just got my Zedboard and I am planning to do a FPGA coprocessing project on it.
I followed the tutorials given and everything went smoothly until Part V.
http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-5
Before applying the given HLS sample code, I am able to send and receive data to and from the FIFO.
However, after generating the new bitstream file from the sample code, the FIFO is not working on both 8-bit and 32-bit.
I have read the tutorial over and over and I realize I have to generate a new boot.bin file according to the bitfile generated.
QUOTING:
Using the bitfile
The bitfile is used as before, when the plain Xillybus bundle was implemented. For PCIe-based platforms, the bitfile is loaded through JTAG to the FPGA (note that the host should be turned off while this is done). If Zedboard is targeted, a new boot.bin file should be generated, based upon the new bitfile, and copied to the SD card like before.
So the problem is that I can't seem to find any tutorial on how to generate boot.bin file from the freshly generated bitfile.
Can anyone help me on this? Just a link or a tutorial will be good for me. Any help would be appreciated very much. Thanks in advanced.
Thanks and best regards.
