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How to import the selected communication Core From Opencores.org website to Vivado Project

bunny23594

Hello everyone,

 

 

I am new to start my career in FPGA design.

 

I want to know that how to import the selected communication Core from opencores.org website to vivado project ?

 

 

Thanking you.

  • 0

    As I expect you may know a simple Google doesn't find much.

     

    I'm a very occasional Viavado user so you would hope to get more help from some others on E14 but first you will need to give us some details.

     

    Which core on opencores.org, what do you want to do with it, what is the overall project, is it a home/hobby thing or work.

     

    As a general rule some work on opencores stuff is usually needed to get it to be useful.

     

    MK

  • 0 in reply to michaelkellett

    Hello,

     

     

    I selected SPI Slave core from opencores.org website.

     

    Now I need to import that core in Vivado (Dont how to do that).

     

    In my project, I am using ZED board (ZYNQ 7020) to implement that selected SPI core to communicate with BRAM in PL part of the ZED board.

     

    BRAM is also work as the shared memory between PL section and PS section of ZED board.

     

    So, I need to write/read some data from ARM cortex (PS section) to the BRAM (PL section) and also I need to read/write some data from BRAM to external device connected with ZED board via selected SPI slave core in PL section.

     

    The external device connected with ZED board will work as SPI Master device but I do not have access to that device. So in my case, I will write test-bench in VHDL that will work as  SPI Master and initiate the clock signal and chip select to select the ZED board as slave device.

     

     

    I hope you understand.

     

    Can you help me answer my query?

     

    Thanking you.

  • 0 in reply to bunny23594

    Have you succeeded in writing anything into the PL and making it work yet ?

     

    Several people on E14 have participated in learning programmes and posted details about how to do this.

     

    I'm assuming you are looking at Santhos G's Verilog spi_slave project.

     

    This is just one Verilog file - so if you can twinkle an LED you can import this  - put it in the right place and add the file to the design in the usual way.

     

    Of course it won't talk to block ram or allocate any IO pins etc without more code to connect it all together.

     

    Could you let us know just how much experience with FPGA s and Vivado you have - I'm not sure where to pitch a reply to help you.

     

    MK

  • 0 in reply to michaelkellett

    Hello,

     

    Thank you for your response.

     

    I am beginner in the FPGA field. I have seen some video on how to write/read (for ex. Hello World!) in BRAM from PS side and that part I understood.

     

    In my project, I do not want to modify the selected core just plug and play.

     

    One more thing, I also need to switch the communication from selected SPI slave in PL section to other communication IP protocol (like I2C, JTAG, SWD). It is like Mux where we can select one comminication core between many and need to develop the generic system concept including BRAM.

     

     

    Can you tell me which project is suitable that include SPI slave core that communicate with BRAM as well ?

     

    Thank you.

  • 0 in reply to bunny23594

    You can't do what you want by "plug and play".

     

    If you want to use an external SPI to talk to a block RAM then I think it is certain that you will need to learn to use the tools properly.

     

    You are starting at the deep end (this is common and many people have been fooled into it by the way the Zynq has been marketed.)

     

    None of the protocols you have mentioned have standard ways of reading and writing to a block of memory - so first you will need to develop your own comms protocol to run on top of them.

     

    What external hardware will be talking to your system ?

     

    If you really have to jump in with Zed then try these free courses.

     

    Announcing FREE Technical Training Courses for Xilinx Embedded Design with MiniZed

     

    I think you might do better with learning VHDl or Verilog on a simple FPGA (Spartan3 or maybe Lattice XP2) first.

     

    There are several sets of detailed blogs about Zynq and Vivado training on E14 - you should have a look at them all.

     

    MK

  • 0 in reply to michaelkellett

    Hi there,

     

    For something like a SPI block, why don't you use the block IP that is built into Vivado?  It is tuned for the chip and created / maintained by Xilinx themselves.

    Using something like that, you just pick the IP from the IP add function in the block design within Vivado.

     

    --Dan