• X Windows to LVDS LCD Display

    Software: Vivado 2019.1, Petalinux 2019.1/

    Hardware: Avnet UltraZED-7EV

     

    I have a project where I need to get an LVDS LCD display working to use as an X-Windows screen.

    Progress to date:

    - The system also has a DisplayPort video stream and that works under…

  • Zynq 7000 Flash Compatibility

    Dear Sir:

     

           I would like to verify the compatibility of the flash, non-volatile, memory that I plan to interface with my Zynq 7000 Avnet Zedboard.

     

           I plan to use a Micron, serial, NOR, flash - N25Q256A.

     

           UG908  asserts that the Micron, manufacturer family…

  • How to prevent copy/cloning of exe file in the SD card?

    Hello,

    We are using a Zedboard with an FMCOMMS3 ( from analog devices) for a detector system. The executable file for standalone mode is in the SD card of the Zedboard. We are planning to send the detector for customer trials and evaluation.

     

    How do we…

  • How to prevent copy/cloning of exe file in the SD card?

    Hello,

    We are using a Zedboard with an FMCOMMS3 ( from analog devices) for a detector system. The executable file for standalone mode is in the SD card of the Zedboard. We are planning to send the detector for customer trials and evaluation. 

     

    How do we…

  • Can't rebuild & update rootfs

    my Compile environment is  ubuntun18.4+vitis 2020.2+petalinux 2020.2,

    my hardware is   AVET's  UltraZedTm PCIe Carrier Card ,

    my BSP package is uz3eg_pciec_base_2020_2.tar.gz.

    Below is my question:

     

    1. I  created the petalinux project,and build, package the project…

  • MiniZed support package for Simulink requires Vivado and SDK 2017?

    Hi All,

     

    I'm trying to install Simulink support for the MiniZed board to try out the Mathworks development workflow. in the "Avnet MiniZed Support Package for Simulink\doc\GettingStarted.mlx document it says that the support package requires Vivado and…

  • How Can I reload the original demo program/FPGA configuration that came installed on my MiniZed board?

    Does anyone know where I would find the original bitstream and demo code that came pre-installed on the MiniZed board?

     

    Thanks in advance for the help and best regards,

    Tom Miller

  • petalinux compile  error

    my Compile environment is  ubuntun18.4+vitis 2020.1+petalinux 2020.1,

    my hardware is   AVET's  UltraZedTm PCIe Carrier Card ,

    my BSP package is uz3eg_pciec_2020_1.tar.

    After  I  created ,configed  the BSP,

    As I compiled the BSP with petalinux-build, below is…

  • Ultra96 V2 JTAG boot mode problem

    Hi.

    I bought Ultra96 V2 development board and the training packet in the https://www.avnet.com/wps/portal/us/resources/training-and-events/event/ultra96-technical-training-courses/ . When I tried to implement SDK applications, i can't boot the board with…

  • How to boundary scan the "PICOZED[7Z020]Rev.E" by use the "FTDI MPSSE[c232hm-ddhsl-0]" with VB6

    I have the PICOZED[7Z020] Rev.E and I need to try for connect it with FTDI MPSSE [JTAG] to VB6 for make the boundary scan.

    Set HIGH/LOW/TRISTATE logic to any pins.

    Could you advice me for start it?

  • ultra96 v2 board pynq overlay problem

    Hello everyone, I am new to pynq ultra96 v2 board. I am going to create a custom about matrix multiplication or simple calculation using Vivado HLS with C or C++.

    But i meet some problem about what data type to use in order to feed the  input array into…

  • PicoZed FMC Carrier Card V2

    I am looking for the tutorials listed on the| Zedboard

     

     

     

    http://picozed.org/support/design/13076/106

    Is there a list of these tutorials that someone would provide a link to?

  • picozed sdr: reboot fails when boot from qspi

    Hi!

     

    We are trying to boot from the qspi nor (32MB) that is embedded on the picozed. When we have por the image is loaded correctly.

    After that, we are using the whole 32MB of the flash.

    When software reset is performed, than the boot rom can't find the fsbl…

  • How to program MicroZed to use dual core

    We are trying to get a little more processing power out of MicroZed and would like to move some of the processing into the 2nd processor. We are using the LWIP and not clear on how to make both processors to work together so we can speedup the processing…

  • Re-initialize USB connection using an interrupt handler

    Dear Forum-members,

     

    I am not sur where to post this question so I chose to first post it here.

     

    I use the microZed as a USB-Device, the microzed itself is programmed to act as controller for a drive.

    Now it oftne happens that the USB-connection between the…

  • Petalinux 2017.4 on Ubuntu 18.04: You system needs to support the en_US.UTF-8 locale.

    I am using Ubuntu 18.04 (running on VirtualBox) and trying to create a Petalinux 2017.4 project to interface a webcam to my Zedboard. I have enabled OpenCV and Python on the project as I'm trying to capture a video stream from my webcam.

    When I run…

  • unable to read file image.ub

    Hi,

    just got my MiniZed and can no longer read the image.ub-file when starting my minized. I was trying to connect it to wifi following: https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Adam-Taylor-s-MicroZed-Chronicles-Part-207-Setting-up-MiniZed…

  • Constraints and bitstream generation

    I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board and familiar with Verilog modules/test bench as beginner. I am using Vivado 2018.2

    I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are…

  • Ultrazed 3EG - display port reference design - desktop linux?

    I've found the displayport reference design for the ultrazed EG I/O carrier.

     

    Where I want to get to is: I have desktop Linux running on the ultrazed with a monitor connected to the displayport. I've seen there is a reference design for the ZCU102,…

  • OpenCV Vitis - Minized

    Hi!

    I have problem linking OpenCV for minized acceleration in Xilinx Vitis.

    Related post: https://forums.xilinx.com/t5/Vitis-SDAccel-and-SDSoC/OpenCV-platform-in-Vitis/td-p/1075256

    BSP: Petalinux - MiniZed packages not visible rootfs

     

    Do you know how can…

  • What Happened To the Speedway Videos

    Just a few weeks ago, there were some great videos by Avnet/Speedway that accompanied the hands-on labs for learning about the Xilinx Zynq 70xx series platforms.  Were the videos moved to a different site/link, or cancelled?  Thanks.

  • Defective MiniZED board

    I just powered up my brand new, out of the box MiniZED board for a webinar.  During the process of using Xilinx's new Vitis environment, When I attempt to JTAG program the device I get the following messages on a console connected to the UART1 console…

  • recreating minized software

    How do I recreate the minized distributed software (including the scripts and the brcmfmac driver)?

    Its based off petalinux 2017.4.

     

    marty

  • How can I control PS MIO GPIOs under PYNQ?

    Hello Everyone,

     

    I see lots of great examples out there of how to control all sorts of hardware under PYNQ using Jupyter Notebooks.

     

    How can I control something seemingly very simple like PS MIO GPIOs from a Jupyter Notebook?

     

    Thanks,

     

    -Kevin

  • AXI Interconnect PS PL on Zynq US+

    Hi everyone,

    I am looking for guidance here:

     

    I need to interface my PS processor (application running on PetaLinux) with an IP created using Vivado HLS. My block design is shown below.

    I just want to pass some data to my IP (sha256), have the calculation…