Hello,

I designed PCB similar to the ultrazed 7 ev series carrier card.

I connect my SATA txp,txn and rxp,rxn same pins with Eval-board.

Also I connect my SATA clk (125mhz) again same pins with Eval-board.

But i can not see any connection with my sata…

Software: Vivado 2019.1, Petalinux 2019.1/

Hardware: Avnet UltraZED-7EV

I have a project where I need to get an LVDS LCD display working to use as an X-Windows screen.

Progress to date:

- The system also has a DisplayPort video stream and that works under…

Is there a boot.bin file that I can get that has the all the IO on the carrier board working?

Thanks,

Rich

Hello!

I have a few questions regarding the real-time cores (Cortex R5F) on the UltraScale+ EV:)

• Can the real-time cores run independently from the rest of the SoC?
• Do the real-time cores can have access to the SD card and CAN peripherals?
• Can the real-time…

Hi,

Recently I started working from a vm to boot the uz3eg from jtag. But sometimes I had the following error: Cannot flush JTAG buffers. After some research, I tried to switch the USB to micro-USB of the uart with the jtag. Since then when I open the…

I'm migrating from the PicoZed SOM to the UltraZed-EV SOM.

In Vivado, I'm trying to configure the DDR for the Zynq UltraScale+ MPSoC. According to the "UltraZed-EV SOM Hardware User Guide" (LIT# UG-AES-ZU7EV-SOM-G-V1.2), the memory is: …

When I bought the UltraZed-EV development board I was told that the software license that comes with it would work with the 2018 / 2019 version of Vivado in perpetuity. However, I went back to the board after putting it down for a long while and the license…

Hello,

I am trying to build petalinux using ./make_uz7ev_evcc.sh

I set both the petalinux and the hdl version to tag 2020p1_uz_petalinux_UZ7EV_EVCC_20201104_065342

I am using Vitis 2020.1.

When the code runs create_petalinux_project(), it fails at

petalinux…

my Compile environment is  ubuntun18.4+vitis 2020.1+petalinux 2020.1,

my hardware is   AVET's  UltraZed PCIe Carrier Card ,

my BSP package is uz3eg_pciec_2020_1.tar.

After  I  created ,configed  the BSP,

As I compiled the BSP with petalinux-build, below is…

I am looking to design a custom carrier board to use with the EV and want to know if it is possible to get the design files to speed up development time?

Thanks,

Rich Arnold

We have two suspected DOA UltraZed-EG SOMs ... what is RMA process.

Our new UltraZrd-EG boards won’t come up on our carrier board (dev kit).

We think the UltraZed is DOA.

Hi,

I've downloaded the UltraZed-Ev platform file from here:

http://zedboard.org/support/design/25481/161

and I ran a synthesis with SDAccel 2019.1 on one of the Xilinx SDAccel example design and I faced the following issue:

WARNING: [Vivado 12-508] No…

Hi Guys Need help,

I just received my Ultrazed-EG starter kit from Avnet. Tried the quick starter instruction card example. Nothing scrolls on terminal screen. I installed SiLab device drivers for Windows 10. Can see two USB to UART terminal 5 & 7. I have…

This is in regards to UltraZed-EV SOM.

Would I be able to build a custom carrier card that brings out the PCIe interface on the PL side?

Hello I'm working with Ultrazed EV carrier card and Ultrazed EV SOM. I can configurate 8t49n241 for generate 148,5MHZ clock for SDI and it works. I also wrote the EEPROM with I2C and it works. And If I manually copy the content of EEPROM in registers…

Hello Everyone,

I have an Avnet  Ultrazed EG IO Carrier Card with SoM. I'm newbie in the field so I decided to follow the attached Getting Started.

I followed all the steps in the UltraZed_EG_Starter_Kit_Tutorial_Vivado_2016_4.pdf.

When I export my bitstream…

Hello,

I was checking ultrazed EG board and found AES-ZU3EG-1-SOM-I-G and AES-ZU3EG-1-SOM-G boards.

after checking data sheet. the only difference is that  the " I " stands for industrial grade.

what is the difference between industrial and extended…

The USB3 through Petalinux 2018.2 in UltraZed-3EG-IO in peripheral mode is not recognized
====================================================================

The parameter is # CONFIG_USB_DWC3_GADGET is not set in the TeraTerm after running the zcat…

I've found the displayport reference design for the ultrazed EG I/O carrier.

Where I want to get to is: I have desktop Linux running on the ultrazed with a monitor connected to the displayport. I've seen there is a reference design for the ZCU102,…

Hi,

How I am defining through PetaLinux (2018.3) the USB3 of the UltraZed-EG, as apparently it doesn’t support the previous setup ( of Ultra96-V1 and V2).

The main command ifconfig usb0 192.168.100.1 netmask 255.255.255.0  and modprobe g_ether

Are not recognized…

Hi everyone,

I am looking for guidance here:

I need to interface my PS processor (application running on PetaLinux) with an IP created using Vivado HLS. My block design is shown below.

I just want to pass some data to my IP (sha256), have the calculation…

Hello Everyone,

We have purchased Zedboard with Avnet Sharp 7 inch Touch Display Kit for our end application. The reference design given was fine and able to program and configure Touch display kit.

https://github.com/Avnet/hdl/tree/zedboard_ali3_sharp…

Hi,

I am testing UltraZed-EG SOM and IO carrier. But I couldn't get PL-SYSCLK (300MHz) working. I put jumper setting to default mode as following;

J1 and J2 placed on pins 1-2 and JP1 is not installed.

I put down simple VHDL test code and xdc file below…

Hi Everyone,

I have a project with Ultra96,

I am using Ubuntu 16.04.3 LTS,VIVADO and SDK 2018.2 and Petalinux 2018.2

When I download ultra96v1_full_2018_2.bsp and install petalinux on ubuntu ( using Virtuabox)

I am implement command :

petalinux-create -t project…