K24 Development Kit - Recent Threads

How to use K24 Syzygy ports when the GTR pins are only mapped to PS?

glenncb — Sun, 14 Dec 2025 23:00:43 GMT

I'm trying to map the K24 IO carrier Syzygy TXR pins but I've hit an issue that I don't know how to work around and wanted to see if anyone has a suggestion. Pins 5-13 and 15 of the Site 1 and Site 2 HSIO ports appear to map to GTR pins which are locked to the PS DisplayPort signals. I though this was a standard SZG TXR port, but it appears to be some custom non-Syzygy port, perhaps only for use with the Avnet provided peripherals? I'm trying to use a 3rd party Syzygy device and I don't see any way to make this work. If there is no workaround, then the HSIO "Syzygy" ports are fairly useless on this board.

Can't access SDCard image linked in 'getting started guide'

jwittrock — Wed, 22 Oct 2025 17:57:25 GMT

The getting started guide provides the following link to an sdcard image

http://avnet.me/k24-dk-prod-base-bsp-sdcard

When trying to access, I get the following .

I have an https://www.avnet.com/ account. Do I need something else?

K24 IO carrier schematics

glenncb — Tue, 27 May 2025 18:50:55 GMT

I would like to get a copy of the K24 IO carrier schematics. The online Getting Started guide indicates this information is available through an Avnet AE, however, I have had no success in getting support.

Does anyone have information on how to obtain the information described in the user guide - specifically schematics and 3D models? I'm not sure why these are not fully available.

Available Documentation

• Getting Started Guide

• Hardware User Guide

• Board Definition Files

• Master User Constraint File

• Net Length Report

• Schematics *

• Bill of Materials*

• Mechanical Drawing *

• 3D Model *

• Carrier Card Source Databases **

* Denotes FAE involvement to gain access to these documents. Contact your local Avnet FAE

Appreciate any help!

-Glenn CB

Petalinux kernel stuck due to rcu warning . Device tree configuration

sam_jones — Fri, 25 Apr 2025 06:55:17 GMT

Hi all,

i have been trying to build petalinux for my custom vivado design. The design contains customs modules that i packaged as IPs and block designs.

An initial run with avnets provided script flow for e.g. "base" were easy to implement. I have followed the steps described in the READ.ME after cloning

# meta-avnet
Yocto layer that can be added on top of a Petalinux Project to add:
- Avnet Machine Configurations
- Avnet Tools and Programs
- Avnet Images, to include extra packages for Avnet boards' rootfs.

To use it:
- clone this repository in the project-spec/ folder inside your Petalinux project
- in Petalinux config, 'Yocto Settings'/'User Layers', add a new layer with '${PROOT}/project-spec/meta-avnet'
- in Petalinux config, change the YOCTO_MACHINE_NAME to use an Avnet Machine ('u96v2-sbc' for example)
- then you can use 'petalinux-build -c avnet-image-minimal' to build your BSP

Petalinux image builds successfully but the boot gets stuck during the kernel stage.

During the build there were error reports about the base design's axi_iic ip in the PL.

components/plnx_workspace/device-tree/device-tree/system-bsp.dtsi:68.1-11 Label or path axi_iic_0 not found
FATAL ERROR: Syntax error parsing input tree

I resolved this by commenting it out in the system-bsp.dtsi under meta-avnet.

/*
&axi_iic_0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;

stts22htr: stts22htr@3f {
compatible = "st,stts22h";
reg = <0x3f>;
};
};
*/

Petalinux log output is posted below. Based on information i have garthered on the internet, this is due to some inconsistencies device tree.

I did not add any of my PL IPs in system-bsp.dtsi. I realised that they are already generated in pl.dtsi .

Thank you so much in advance for your support.

Ps error out

sam_jones — Fri, 07 Mar 2025 00:52:58 GMT

Hello,

i received a K24 board today and started started a bring up.

Unfortunately PS Error Out turns on once i power on the board. This occurs regardless of the boot source (i.e. SD card / QSPI).

I understand that PS Error out could be most probably triggered by the PMU. Is there a way to read the PMU error signals ?

Has anyone encountered a similar scenario ?

Thanks & regards

Reference design

eeskbala — Thu, 06 Mar 2025 11:40:51 GMT

Hi,

We have managed to download the WIC file from the Avnet product page

https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/k24-development-kit

However, could you please let us know where to find the relevant design files (Vivado, Vitis/BSP) we can use to generate the image ourselves?

We found the board definition files here, https://github.com/Avnet/bdf

Also, useful will be the version of Vivado used for building this reference design? 2023.2 or 2024.1 or something else?

Regards