K24 Development Kit - Recent Threads

RE: How to use K24 Syzygy ports when the GTR pins are only mapped to PS?

iksevas — Wed, 17 Dec 2025 16:10:46 GMT

There are 28 I/O that make up SYZYGY STANDARD PINOUT (Not accounting for 2x clock pairs and I2C). There are 18 I/O that make up a SYZYGY TXR PINOUT (not accounting for 2x clock pairs and I2C). That converter board should be relatively simple. The NET LENGTH report for the KIT shows that the length to the two TXR sites are tuned, so you should be able to length tune the conversion from TXR to STD to maintain performance if desired.

It's difficult to design a product to get the most available features that will work for the majority of people. That's the challenge with expansion interface specifications in general. My assumption / expectation is that people would develop their own add-on cards for quick prototyping, ie - like this converter board for you to mate to an off-the-shelf solution or a custom add-on card to bolt onto the one or both of the expansion connectors with whatever custom interface they can think of.

An option for you could have been ZUBoard if you were targeting the STANDARD port as it has one of them on the board. This takes you away from the K24 SOM though. The K24 Development Kit was designed with ZUBoard as the form factor and there simply was not enough I/O to make a STADNARD port from.

How to use K24 Syzygy ports when the GTR pins are only mapped to PS?

glenncb — Sun, 14 Dec 2025 23:00:43 GMT

I'm trying to map the K24 IO carrier Syzygy TXR pins but I've hit an issue that I don't know how to work around and wanted to see if anyone has a suggestion. Pins 5-13 and 15 of the Site 1 and Site 2 HSIO ports appear to map to GTR pins which are locked to the PS DisplayPort signals. I though this was a standard SZG TXR port, but it appears to be some custom non-Syzygy port, perhaps only for use with the Avnet provided peripherals? I'm trying to use a 3rd party Syzygy device and I don't see any way to make this work. If there is no workaround, then the HSIO "Syzygy" ports are fairly useless on this board.

RE: How to use K24 Syzygy ports when the GTR pins are only mapped to PS?

glenncb — Wed, 17 Dec 2025 15:47:06 GMT

I was trying to connect a Digilent ADC 1410 module to the site 1 port, using a custom PCB to convert from the Syzygy-TXR connector to the Syzygy-STD connector. There were 10 pins on the port hard wired to the PS GTR pins. The rest appear to be useable. The chart below shows the conflicting GTR pins:

The pins in red are the conflicting ones. To workaround the issue, I'm developing a custom PCB to remap pins from Site 1 + Site 2 to a single Syzygy-STD port by mapping those pins in conflict to non conflicting pins from Site 2. That should give me one usable Syzygy-STD port until I can design my own custom carrier.

The trace length for the pins coming from Site2 will be substantially longer, so probably not useable for any high speed signals but should be ok for the Digilent ADC as those pins are mostly low speed controls (gain, ac coupling, etc).

-GlennCB

RE: How to use K24 Syzygy ports when the GTR pins are only mapped to PS?

iksevas — Wed, 17 Dec 2025 03:33:54 GMT

What are you trying to map to these ports? The K24 module does not contain PL based transceivers. Only GTR transceivers map to this MPSoC. You will be limited to implementations of the GTRs, ie PCIe, Display Port, USB3, SATA.

RE: Reference design

glenncb — Sun, 14 Dec 2025 21:37:17 GMT

BTW - I found the answer but it wasn't super obvious to me so I thought I would share. I didn't realize the BSP file is actually a compressed tar archive which contains everything including the complete Vivado project, block diagram, XPR file, Petalinux image files, etc. Just download the BSP file and extract it. You can rename the bsp extension to ".tar.xz" (as it is a tarred XZ compressed image) and you should be able to extract it under either Windows or Linux. Iksevas is correct above - just download the BSP from the github/Avnet repo.

Reference design

eeskbala — Thu, 06 Mar 2025 11:40:51 GMT

Hi,

We have managed to download the WIC file from the Avnet product page

https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/k24-development-kit

However, could you please let us know where to find the relevant design files (Vivado, Vitis/BSP) we can use to generate the image ourselves?

We found the board definition files here, https://github.com/Avnet/bdf

Also, useful will be the version of Vivado used for building this reference design? 2023.2 or 2024.1 or something else?

Regards

Can't access SDCard image linked in 'getting started guide'

jwittrock — Wed, 22 Oct 2025 17:57:25 GMT

The getting started guide provides the following link to an sdcard image

http://avnet.me/k24-dk-prod-base-bsp-sdcard

When trying to access, I get the following .

I have an https://www.avnet.com/ account. Do I need something else?

RE: Can't access SDCard image linked in 'getting started guide'

iksevas — Wed, 29 Oct 2025 21:04:38 GMT

jwittrock- Try this link and let me know if this will work for you.

RE: Can't access SDCard image linked in 'getting started guide'

iksevas — Wed, 29 Oct 2025 21:01:52 GMT

avtinc.sharepoint.com/.../EiaBzfDkDr9Jo2OQN52zoQsBD1RGDqBHt5ma10J1sUihUw

RE: Can't access SDCard image linked in 'getting started guide'

cstanton — Tue, 28 Oct 2025 23:19:41 GMT

Most of these files appear to be hosted on sharepoint, perhaps it's worth talking with the e14 community dev' or community business team to have them hosted somewhere more accessible?

RE: Can't access SDCard image linked in 'getting started guide'

iksevas — Mon, 27 Oct 2025 15:44:10 GMT

I will look into this for you. Sorry about the delay. I’m just seeing this.

RE: Reference design

lightcollector — Sat, 25 Oct 2025 04:13:39 GMT

Hi, The specific repo is https://www.github.com/Avnet/hdl. This contains tcl scripts that put together a Vivado project for all of the Avnet/Tria boards. Avnet/Tria does not have a repo with direct Vivado project xpr files for the board you asked about. Please make sure you select the correct github version branch for the tools version you are using.

RE: K24 IO carrier schematics

iksevas — Tue, 21 Oct 2025 06:28:21 GMT

Can you message me offline so that I can get you some proper help here? Those documents with an asterisk do require FAE support. Challenge will be FAEs are bandwidth limited and may not respond as quickly as you need.

K24 IO carrier schematics

glenncb — Tue, 27 May 2025 18:50:55 GMT

I would like to get a copy of the K24 IO carrier schematics. The online Getting Started guide indicates this information is available through an Avnet AE, however, I have had no success in getting support.

Does anyone have information on how to obtain the information described in the user guide - specifically schematics and 3D models? I'm not sure why these are not fully available.

Available Documentation

• Getting Started Guide

• Hardware User Guide

• Board Definition Files

• Master User Constraint File

• Net Length Report

• Schematics *

• Bill of Materials*

• Mechanical Drawing *

• 3D Model *

• Carrier Card Source Databases **

* Denotes FAE involvement to gain access to these documents. Contact your local Avnet FAE

Appreciate any help!

-Glenn CB

RE: K24 IO carrier schematics

jwittrock — Mon, 20 Oct 2025 11:02:18 GMT

I have just received my kit and would also like schematic set.

Thanks,

jwittrock

RE: Reference design

glenncb — Mon, 13 Oct 2025 19:17:57 GMT

I'm specifically looking for the vivado project (xpr) file, block design, etc. All I have been able to find are the board definition, constraints, etc. Can anyone point me to the area which has the actual Vivado project files?

RE: K24 IO carrier schematics

iksevas — Thu, 02 Oct 2025 20:17:37 GMT

answered request DM.

RE: K24 IO carrier schematics

marccyr — Thu, 02 Oct 2025 19:07:32 GMT

messaging you as well for the same needs

RE: K24 IO carrier schematics

marccyr — Thu, 02 Oct 2025 19:07:03 GMT

I am also looking for schematics and 3D model. Any progress in the last 4 months?

RE: K24 IO carrier schematics

iksevas — Fri, 30 May 2025 23:17:43 GMT

Petalinux kernel stuck due to rcu warning . Device tree configuration

sam_jones — Fri, 25 Apr 2025 06:55:17 GMT

Hi all,

i have been trying to build petalinux for my custom vivado design. The design contains customs modules that i packaged as IPs and block designs.

An initial run with avnets provided script flow for e.g. "base" were easy to implement. I have followed the steps described in the READ.ME after cloning

# meta-avnet
Yocto layer that can be added on top of a Petalinux Project to add:
- Avnet Machine Configurations
- Avnet Tools and Programs
- Avnet Images, to include extra packages for Avnet boards' rootfs.

To use it:
- clone this repository in the project-spec/ folder inside your Petalinux project
- in Petalinux config, 'Yocto Settings'/'User Layers', add a new layer with '${PROOT}/project-spec/meta-avnet'
- in Petalinux config, change the YOCTO_MACHINE_NAME to use an Avnet Machine ('u96v2-sbc' for example)
- then you can use 'petalinux-build -c avnet-image-minimal' to build your BSP

Petalinux image builds successfully but the boot gets stuck during the kernel stage.

During the build there were error reports about the base design's axi_iic ip in the PL.

components/plnx_workspace/device-tree/device-tree/system-bsp.dtsi:68.1-11 Label or path axi_iic_0 not found
FATAL ERROR: Syntax error parsing input tree

I resolved this by commenting it out in the system-bsp.dtsi under meta-avnet.

/*
&axi_iic_0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;

stts22htr: stts22htr@3f {
compatible = "st,stts22h";
reg = <0x3f>;
};
};
*/

Petalinux log output is posted below. Based on information i have garthered on the internet, this is due to some inconsistencies device tree.

I did not add any of my PL IPs in system-bsp.dtsi. I realised that they are already generated in pl.dtsi .

Thank you so much in advance for your support.

Ps error out

sam_jones — Fri, 07 Mar 2025 00:52:58 GMT

Hello,

i received a K24 board today and started started a bring up.

Unfortunately PS Error Out turns on once i power on the board. This occurs regardless of the boot source (i.e. SD card / QSPI).

I understand that PS Error out could be most probably triggered by the PMU. Is there a way to read the PMU error signals ?

Has anyone encountered a similar scenario ?

Thanks & regards

RE: Ps error out

iksevas — Wed, 09 Apr 2025 19:03:18 GMT

What SD card did you end up using? I feel like the MPSoCs want something on the smaller side and to SDHC in the class 10 range for robustness. I do know that SDXC is has been a no-no.

RE: Ps error out

sam_jones — Wed, 09 Apr 2025 15:29:45 GMT

If anyone is facing a similar issue , i would recommend that you have a look at your sd card. Otherwise check boot partitioning on sdcard before using balena etcher.

RE: Reference design

iksevas — Thu, 03 Apr 2025 20:59:17 GMT

Also, the K24 is fairly new so it is only supported in 2023.2, 2024.1 and 2024.2 branches.