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uZed Development Display Core

Former Member

Hello,

I am trying to reuse the IP core provided with the 7" LCD development display for a current project. The reference design has everything required for this project and doing electrical adaptations instead of firmware mods will save a lot of time. Is there any documentation on this because the reference design is mixed verilog and VHDL. I only know VHDL. What exactly is video protocol output to the PMOD connectors? It seems to be VGA run over LVDS?

  • 0

    Hi neg_ion,

    The only thing special about the IP core is that it provides a way to provide video pixel data to the core via the Xilinx VDMA core.  Think of this as the processor interface.

    The IP core then provides the timing and logic to generate the video data encoding, horizontal/vertical frame syncs, and serialize the output via the OSERDES FPGA primatives.  Think of this as this end as the panel interface.

    The IP core then connects the OSERDES to our 3.3V I/O Pmod banks via FPGA pins set with the TMDS_33 I/O standard.  The Pmod provides a level translation of the TMDS_33 signal to create the LVDS levels that the Sharp 7" panel is looking for.

    You can see the pixel data encoding format (I believe that it is RGBA by default) used by this panel by looking at the Sharp datasheet:

    http://www.sharpsme.com/download/LQ070Y3LG4Apdf

    Regards,

    -Kevin

  • 0 in reply to zedhed

    OK thanks a lot. This is really helpful. Would it be safe to say I could use the output video signals directly as DVI-D due to it being TMDS_33 output from the Zynq? Is the information output from the Zynq core compatible with DVI-D monitor standards?