Actions
Forum Thread Details
  • State Verified Answer
  • Replies 5 replies
  • Subscribers 265 subscribers
  • Views 356 views
  • Users 0 members are here
Related

Creating a MIG Block for microZed-020

bkamen

Another toss-up of this topic list or the Xilinx Tools list...

Has anyone created a MIG block to split off the 1G DDR3 from the PS for use by PL designs?

This is my first time running the MIG and I have questions like:

* Ok, we set the Controller Options memory type which is x16, but then there's a pull-down box asking for 8/16/32/64bit Data Width.

* AXI Parameters: Data Width: 32 or 64? Arbitration Scheme?

* Memory Options: Input Clock Period defaults to 11250pS. Should this be changed? What about any additional clocks? (and then the options below?)

* FPGA Options: ANything needing changing here? (I already have an XADC)

Extended FPGA Options: uZed020 says 40ohms?

Pin Selection: (ugh. Anyone got a UCF file they'd share?)

Etc...etc...

Thanks,

 -Ben


EDIT: now that I'm closely reading this.. I'm wondering if the MIG is only useful for memory attached to PL available pins (i.e. the MIG won't work for PS controller attached memory?)

Parents
  • 0

    Hey Josh,

    Excellent! Thanks...

    Both of those definitively confirm what I was already thinking -- and also end up leaving another question for which I could use some advice.

    So I'm using a OnSemi VITA (and eventually Python) image sensor for which I'm creating an ROI cropping engine...

    I need buffer space for 2 frames @ 1,313,280bytes each. I'm looking at AXI based DMA to the PS and the memory attached to it.

    How hands-off or hands-on does the OS running on the PS need to be to let the FPGA do it's thing?

    Also, any pointers at good AXI-DMA examples for the uZed-020? There's some setup questions there that an example would be nice to have.


    thanks,

     -Ben

Reply
  • 0

    Hey Josh,

    Excellent! Thanks...

    Both of those definitively confirm what I was already thinking -- and also end up leaving another question for which I could use some advice.

    So I'm using a OnSemi VITA (and eventually Python) image sensor for which I'm creating an ROI cropping engine...

    I need buffer space for 2 frames @ 1,313,280bytes each. I'm looking at AXI based DMA to the PS and the memory attached to it.

    How hands-off or hands-on does the OS running on the PS need to be to let the FPGA do it's thing?

    Also, any pointers at good AXI-DMA examples for the uZed-020? There's some setup questions there that an example would be nice to have.


    thanks,

     -Ben

Children
No Data