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Generate Clock for PL output on FMC connector.

Former Member

Hello,

I would like to generate a clock and use it as a PL output on the FMC connector for the FMC CC board.
I'm using VIvado but I get multiple errors related to 'iostandard' and 'PACKAGE PIN' properties.
I'd highly appreciate any suggestions/sample projects that can help solve this issue.

  • 0

    The 'iostandard' and 'PACKAGE PIN' properties are typically set in the constraints file. You need to look at what you have set the Bank voltage to be in hardware on the FMC then make sure that your IOSTANDARD setting in your constraints file for all signals in that bank are compatible with that voltage.

     

    Likewise, you should use the constraint file to set the specific I/O pin where you are sending the clock.

     

    Bryan

  • 0

    Hi Bryan,

    Thank you for the suggestion. I'm using the predefined IP on Vivado and its PS clock, so I can't really modify the .xdc file for the Zynq processing_system.
    All I want to do is to generate a clock on the PS side and route it through an IO on the PL side.
    I'm generating a wrapper for the IP core and connecting it on a top  module to an IO on the PL side but it doesn't seem to work.

    Thanks

  • 0

    Even if you are generating the clock through the PS, as soon as you route it into the PL and out a PL I/O, then you have to adhere to PL design guidelines, which includes setting the IOSTANDARD and pin location in a constraints file. You can skip setting the timing constraint as the tools will recognize the timing constraint to apply based on your PS clock settings.

     

    Bryan