MicroZed Hardware Design - Recent Threads

Microzed 7020 Device Tree

dwoods105 — Thu, 30 Oct 2025 21:39:27 GMT

Hello,

I have a 7020 Microzed. I am currently building the image with Yocto with the Gen-Machine-Conf Parse-SDT workflow from AMD.

I am attempting to get the USB PHY to work. I would like to to be in peripherial mode, but I can't get it working at all.

Gen-Machine-conf gives me the standard device tree files, and I am using a custom DTSI that is included in the system-top.

Does anyone know what I'm doing wrong?

/dts-v1/;
#include "zynq-7000.dtsi"
#include "pl.dtsi"
#include "pcw.dtsi"
/ {
	device_id = "7z020";
	slrcount = <1>;
	family = "Zynq";
	speed_grade = "1";
	VIPER_FPGA_PIXBUF_memory: memory@40000000 {
		compatible = "xlnx,axi-bram-ctrl-4.1";
		xlnx,ip-name = "axi_bram_ctrl";
		device_type = "memory";
		memory_type = "memory";
		reg = <0x40000000 0x200000>;
	};
	VIPER_FPGA_REGS_memory: memory@80000000 {
		compatible = "xlnx,axi-bram-ctrl-4.1";
		xlnx,ip-name = "axi_bram_ctrl";
		device_type = "memory";
		memory_type = "memory";
		reg = <0x80000000 0x80000>;
	};
	ps7_qspi_linear_0_memory: memory@fc000000 {
		compatible = "xlnx,ps7-qspi-linear-1.00.a-memory";
		xlnx,ip-name = "ps7_qspi_linear";
		device_type = "memory";
		memory_type = "linear_flash";
		reg = <0xfc000000 0x1000000>;
	};
	ps7_ddr_0_memory: memory@00100000 {
		compatible = "xlnx,ps7-ddr-1.00.a";
		xlnx,ip-name = "ps7_ddr";
		device_type = "memory";
		memory_type = "memory";
		reg = <0x00100000 0x3FF00000>;
	};
	ps7_ram_0_memory: memory@0 {
		compatible = "xlnx,ps7-ram-1.00.a";
		xlnx,ip-name = "ps7_ram";
		device_type = "memory";
		memory_type = "memory";
		reg = <0x0 0x30000>;
	};
	ps7_ram_1_memory: memory@ffff0000 {
		compatible = "xlnx,ps7-ram-1.00.a";
		xlnx,ip-name = "ps7_ram";
		device_type = "memory";
		memory_type = "memory";
		reg = <0xffff0000 0xfe00>;
	};
	chosen {
		stdout-path = "serial0:115200n8";
	};
	aliases {
		serial0 = &uart1;
		spi0 = &qspi;
		serial1 = &coresight;
		spi1 = &VIPER_TRIGDAC_SPI;
		spi2 = &VIPER_ADC_SPI;
		ethernet0 = &gem0;
	};
	cpus_a9: cpus-a9@0 {
		compatible = "cpus,cluster";
		address-map = <0xf0000000 &amba 0xf0000000 0x10000000>, 
			      <0x40000000 &VIPER_FPGA_PIXBUF_memory 0x40000000 0x200000>, 
			      <0x40000000 &VIPER_FPGA_PIXBUF 0x40000000 0x200000>, 
			      <0x80000000 &VIPER_FPGA_REGS_memory 0x80000000 0x80000>, 
			      <0x80000000 &VIPER_FPGA_REGS 0x80000000 0x80000>, 
			      <0x00100000 &ps7_ddr_0_memory 0x00100000 0x3FF00000>, 
			      <0x0 &ps7_ram_0_memory 0x0 0x30000>, 
			      <0xffff0000 &ps7_ram_1_memory 0xffff0000 0xfe00>, 
			      <0x40200000 &axi_gpio_0 0x40200000 0x10000>, 
			      <0x81e00000 &VIPER_ADC_SPI 0x81e00000 0x10000>, 
			      <0x81e10000 &VIPER_TRIGDAC_SPI 0x81e10000 0x10000>, 
			      <0x83c00000 &axi_xadc_0 0x83c00000 0x10000>, 
			      <0xf8008000 &ps7_afi_0 0xf8008000 0x1000>, 
			      <0xf8009000 &ps7_afi_1 0xf8009000 0x1000>, 
			      <0xf800a000 &ps7_afi_2 0xf800a000 0x1000>, 
			      <0xf800b000 &ps7_afi_3 0xf800b000 0x1000>, 
			      <0xf8800000 &coresight 0xf8800000 0x100000>, 
			      <0xf8006000 &mc 0xf8006000 0x1000>, 
			      <0xf8007000 &devcfg 0xf8007000 0x100>, 
			      <0xf8004000 &ps7_dma_ns 0xf8004000 0x1000>, 
			      <0xf8003000 &dmac_s 0xf8003000 0x1000>, 
			      <0xe000b000 &gem0 0xe000b000 0x1000>, 
			      <0xf8f00200 &global_timer 0xf8f00200 0x100>, 
			      <0xe000a000 &gpio0 0xe000a000 0x1000>, 
			      <0xf8900000 &ps7_gpv_0 0xf8900000 0x100000>, 
			      <0xf8f01000 &intc 0xf8f01000 0x1000>, 
			      <0xe0200000 &ps7_iop_bus_config_0 0xe0200000 0x1000>, 
			      <0xf8f02000 &L2 0xf8f02000 0x1000>, 
			      <0xf800c000 &ps7_ocmc_0 0xf800c000 0x1000>, 
			      <0xf8891000 &ps7_pmu_0 0xf8891000 0x1000>, 
			      <0xe000d000 &qspi 0xe000d000 0x1000>, 
			      <0xfc000000 &ps7_qspi_linear_0_memory 0xfc000000 0x1000000>, 
			      <0xf8f00000 &ps7_scuc_0 0xf8f00000 0xfd>, 
			      <0xf8f00600 &scutimer 0xf8f00600 0x20>, 
			      <0xf8f00620 &scuwdt 0xf8f00620 0xe0>, 
			      <0xe0100000 &sdhci0 0xe0100000 0x1000>, 
			      <0xf8000000 &slcr 0xf8000000 0x1000>, 
			      <0xe0001000 &uart1 0xe0001000 0x1000>, 
			      <0xe0002000 &usb0 0xe0002000 0x1000>, 
			      <0xf8007100 &adc 0xf8007100 0x21>;
		#ranges-address-cells = <0x1>;
		#ranges-size-cells = <0x1>;
	};
};
#include "VM_Latest_V24p2_NHW.dtsi"

Thanks in advance!

// SPDX-License-Identifier: GPL-2.0
/*
 * USB peripheral fix for Avnet MicroZed (Zynq-7000)
 * Keeps baseline bootability while correcting ULPI PHY definition.
 */

 /include/ "zynq-7000.dtsi"

/ {
	model = "Avnet MicroZed board";
	compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000";

	amba: amba {
		usb0: usb@e0002000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			reg = <0xe0002000 0x1000>;
			interrupt-parent = <&intc>;
			interrupts = <0 21 4>;
			clocks = <&clkc 28>;
			dr_mode = "peripheral";
			usb-phy = <&usb_phy0>;
			status = "okay";
		};

		usb_phy0: phy0 {
			compatible = "ulpi-phy";
			#phy-cells = <0>;
			view-port = <0x170>;
			drv-vbus;
		};
	};

	aliases {
		ethernet0 = &gem0;
		serial0 = &uart1;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	chosen {
		bootargs = "earlycon";
		stdout-path = "serial0:115200n8";
	};
};

&clkc {
	ps-clk-frequency = <33333333>;
};

&gem0 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-handle = <&ethernet_phy>;

	ethernet_phy: ethernet-phy@0 {
		reg = <0>;
	};
};

&sdhci0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

How to perform DDR3 PCB layout for Xilinx FPGA, MicroZed provides any layout/gerber files?

rajhlinux — Tue, 15 Jul 2025 04:20:25 GMT

Any PCB Layout/gerber files for MicroZed, so that I can get a good understanding in laying out the DDR3 traces on PCB? My goal is to learn how to layout DDR3 traces to an FPGA, I can't find any sources that teaches in detailed in how to do so and reading just a text document such as design reference documentation is not too helpful.

I found this link which contains a PDF of "Mechanical drawings" for MicroZed:

https://www.avnet.com/americas/products/avnet-boards/avnet-board-families/microzed/

https://www.avnet.com/wcm/connect/2908a4d7-4434-49ca-b37d-661551898d68/PRJ-US2SOM-1-01-03-PDF3D.PDF?MOD=AJPERES&CACHEID=ROOTWORKSPACE-2908a4d7-4434-49ca-b37d-661551898d68-nDjeMQQ

However, the CAD file being rendered in PDF format, seems to be for a different board other than MicroZed board. The CAD PDF file only works with Acrobat Reader and is super slow to render (I have a beefy NVIDIA RTX 3080 TI GPU).

It is extremely tricky to view the layers. Any guide in how to properly operate this CAD PDF file to view the DDR3 PCB traces?

Thanks for any info.

Ethernet PHY problems on MicroZed rev. H

rgaddi — Tue, 17 Jun 2025 16:43:06 GMT

I'm having intermittent problems communicating with the Marvell Ethernet PHY on the MicroZed. Very possibly the same problem as Microzed 7Z010 rev H having intermittent Ethernet issues a year ago.

According to the system message log, and confirming with mii-diag and phy-tool, it looks like it's failing to find the PHY. My hunch is that it's a continuation of the same reset problem seen on previous MicroZed revisions.

If I It will usually identify the PHY correctly and communicate with it from a very cold boot, like it's been off for half an hour cold boot. And will often keep finding it through several power cycles after that. But at some point it'll stop finding the PHY, and one it does the PHY is lost for however many more quick power cycles. But then if I get a grounded wire and hold PG_MODULE low externally (which is the only thing on the board that triggers a PHY reset) then all of a sudden the PHY works and keeps working.

I've got the MicroZed connected to a custom carrier; that carrier only monitors PG_MODULE and does not drive it.

Some units with this intermittent failure went into the field, and are now failing intermittently at customer sites, so we've got a real problem. I have no way of identifying which MicroZeds will and will not show the problem because again, it's intermittent. So my not having seen a given unit fail yet means nothing.

MicroZed PetaLinux 2023.2 spidev transfer timed out

acountryman25 — Mon, 19 May 2025 19:53:47 GMT

This question has also been posted to the AMD Adaptive Support forums (https://adaptivesupport.amd.com/s/question/0D5KZ00000pAdsk0AC/zynq-7000-petalinux-20232-spidev-transfer-timed-out).

The team I am a member of is currently working on upgrading a project we inherited from the 2014 tools (Vivado, PetaLinux, etc) to the 2023.2 tools. This project uses PetaLinux running on an Avnet MicroZed AES-Z7MB-7Z020-SOM-G (XC7Z020-1CLG400C). We have encountered an issue with SPI 1 that we have not been able to resolve ("spidev spi1.X: SPI transfer timed out", "spi_master spi1: failed to transfer one message from queue", the state of the SPI 1 pins/signals has been checked and they are in their idle state with no activity observed).

The PetaLinux 2023.2 project was created using the scripts/make_mz7020_som_base.sh script from the Avnet petalinux GitHub repository's 2023.2 branch. The following changes have been made to the petalinux and meta-avnet repositories:

Made various modifications so that the build can be performed without internet access.
Made the following build configuration changes:
- Changed BOOT_METHOD to INITRD
- Set BOOT_SUFFIX to _MINIMAL
- Set INITRAMFS_IMAGE to petalinux-image-minimal
Removed axi_intc_0 and amba_pl entries from meta-avnet/recipes-bsp/device-tree/files/mz/system-bsp.dtsi to fix rebuild errors that occur when the XSA file is swapped out for the one from our Vivado project.

SPI transfers are done using SPI_IOC_MESSAGE ioctl() calls.

SPI 1 is configured as follows in Vivado:

SPI 1 is enabled and is configured to use MIO 10 .. 15
- MIO 10:
  - Signal: mosi
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: disabled
  - Direction: inout
- MIO 11:
  - Signal: miso
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: enabled
  - Direction: inout
- MIO 12:
  - Signal: sclk
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: disabled
  - Direction: inout
- MIO 13:
  - Signal: ss[0]
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: enabled
  - Direction: inout
- MIO 14:
  - Signal: ss[1]
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: enabled
  - Direction: out
- MIO 15:
  - Signal: ss[2]
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: enabled
  - Direction: out

dtsi SPI 1 configuration overrides:

&spi1 {
    status = "okay";
    num-cs = <3>;
    is-decoded-cs = <0>;
    speed-hz=<10000000>;
 
    device@0{
        status = "okay";
        compatible="rohm,dh2228fv";   // Not actually this device, workaround to get /dev/spidev1.0 to appear.
        reg=<0>;                      // Chipselect 0
        spi-max-frequency=<10000000>; // 10 Mhz
    };
 
    device@1{
        status = "okay";
        compatible="rohm,dh2228fv";   // Not actually this device, workaround to get /dev/spidev1.0 to appear.
        reg=<1>;                      // Chipselect 1
        spi-max-frequency=<10000000>; // 10 Mhz
    };
 
    device@2{
        status = "okay";
        compatible="rohm,dh2228fv";   // Not actually this device, workaround to get /dev/spidev1.0 to appear.
        reg=<2>;                      // Chipselect 2
        spi-max-frequency=<10000000>; // 10 Mhz
    };
};

SPI 1 device tree entry from decompiled DTB:

spi@e0007000 {
    compatible = "xlnx,zynq-spi-r1p6";
    reg = <0xe0007000 0x1000>;
    status = "okay";
    interrupt-parent = <0x04>;
    interrupts = <0x00 0x31 0x04>;
    clocks = <0x01 0x1a 0x01 0x23>;
    clock-names = "ref_clk\0pclk";
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    num-cs = <0x03>;
    is-decoded-cs = <0x00>;
    speed-hz = <0x989680>;
    phandle = <0x24>;
 
    device@0 {
        status = "okay";
        compatible = "rohm,dh2228fv";
        reg = <0x00>;
        spi-max-frequency = <0x989680>;
    };
 
    device@1 {
        status = "okay";
        compatible = "rohm,dh2228fv";
        reg = <0x01>;
        spi-max-frequency = <0x989680>;
    };
 
    device@2 {
        status = "okay";
        compatible = "rohm,dh2228fv";
        reg = <0x02>;
        spi-max-frequency = <0x989680>;
    };
};

We have tried the following to resolve this issue but they were not successful:

Disabling power management in the kernel configuration as suggested by some adaptivesupport posts
Increasing the timeout period as was done for https://adaptivesupport.amd.com/s/article/2021-Zynq-7000-Zynq-MPSoC-Versal-Yocto-PetaLinux-kernel-driver-fails-to-configure?language=en_US
Changing the SPI 1 interrupts configuration (<0 49 4>) to the configuration that was used in the old device tree (<0 49 0>)

Any suggestions for resolving this issue would be greatly appreciated.

Avnet MicroZed Product Compliance

DarrylPonting — Thu, 24 Apr 2025 10:08:45 GMT

Hello

I have been directed to these forums by Avnet to ask about Product compliance. I am trying to determine the RoHS and REACH compliance of the MicroZed, specifically AES-Z7MB-7Z020-SOM-I-G Rev H. I can see the RoHS compliance is quite clear, however everywhere seems to list REACH as TBA.

Hopefully someone here can help.

Thanks

Where to start: MicroZed 7020, Vivado 2024.2, Ubuntu 24.04

eNtropy618 — Sat, 05 Apr 2025 17:47:29 GMT

Hello,

Can someone please point me in the right direction for getting started developing for the PS and PL using systemverilog & verilog, using Vivado 2024.2 on Ubuntu 24.04? I haven't touched an FPGA in 10 years, and I'm hoping this board is still supported. Some of the documentation I found so far points to dead links for support or reference. I was able to get Vivado installed following the instructions found at https://gist.github.com/aitesam961/51a8dd9b785d0cc9f0bed5faf51e982e, using whatever free amd/xilinx license came with the Vivado local installer. I have a small "JTAG-HS3 Rev. A" board that I'm using to interface with the Zynq board (note: I only have the small dev board, not the expansion board that it plugs into to expose all pins to the user's possible different use cases). When I connect it via USB to my computer, and connect another usb-micro cable between my computer and the board's own micro usb port for power, I'm able to see my board in the Vivado Hardware manager.

In the Vivado hardware manager, with the board connected, it says "Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it." I can click Program Device, but I don't know what to load into it.

If someone could just point me in the direction of the best documentation to read to get familiar again with this process, that would be awesome. I've never actually used this board for FPGA development (the Zynq 7020 dev board may be old now, but it's new to me), and only briefly touched on VHDL about 10+ years ago like I said. I want to switch from VHDL to Verilog, but need to study up on it. I also don't remember how to use Vivado.

Thank you,

Rich C.

Are the PCB and Schematic design files available for the MicroZed AES-Z7MB-7Z010-SOM-I-G/REV-H ?

byoung — Wed, 02 Apr 2025 12:56:20 GMT

Are the PCB and Schematic design files available for the MicroZed AES-Z7MB-7Z010-SOM-I-G/REV-H ?

What CAD program was used, Altium?

USB0 USB-ETH adapter MicroZed Zynq 7010 board

marc.jofre — Sat, 29 Mar 2025 16:52:22 GMT

Hi all,

I am trying to use a USB-to-ETH adapter connected on USB0 Microzed Zynq 7010.

I am using linux-xlnx patched with PREEMPT_RT.

The adapter is based on an Asix AX88279 chip (drivers): www.asix.com.tw/.../AX88279

I have to comment out some function calls in the Asix usb driver in order for petalinux to compile. Apparently, this calls are in places of the code for newer kernel versions.

The board is able to detect the device in the USB bus, with the module divers and as an Ethernet interface:

[ 291.783700] ax_usb_nic: loading out-of-tree module taints kernel.

[ 291.787981] usbcore: registered new interface driver ax_usb_nic

[ 291.807362] ax_usb_nic 1-1:1.0: ASIX AX88279 USB Ethernet Controller 3.4.0 (1.2.0.4_7.1)

root@AvnetMicroZedproj7010:~# lsusb | grep -i -e "Ethernet" -e "Wireless"

Bus 001 Device 002: ID 0b95:1790 ASIX Electronics Corp. AX88179 Gigabit Ethernet

The information on the driver module:

root@AvnetMicroZedproj7010:~# modinfo /lib/modules/6.6.40-rt51-xilinx-g2b7f6f70a62a-dirty/home/marcjofre/Scripts/AvnetMicroZedproj7010/build/tmp/work-shared/zynq-generic-7z010/kernel-source/drivers/net/usb/ax_usb_nic.ko

filename: /lib/modules/6.6.40-rt51-xilinx-g2b7f6f70a62a-dirty/home/marcjofre/Scripts/AvnetMicroZedproj7010/build/tmp/work-shared/zynq-generic-7z010/kernel-source/drivers/net/usb/ax_usb_nic.ko

version: 3.4.0

license: GPL

description: ASIX USB Ethernet Controller

author: ASIX

srcversion: 757126603A9CAE69242D9C0

alias: usb:v0B95p1790d0[0-3]*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0B95p1790d0400dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0B95p1790d0[0-1]*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0B95p1790d0200dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0B95p1790d0[0-2]*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0B95p1790d0300dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0711p0179d00*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0711p0179d0100dc*dsc*dp*ic*isc*ip*in*

alias: usb:v2001p4A00d00*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v2001p4A00d0100dc*dsc*dp*ic*isc*ip*in*

alias: usb:v04E8pA100d00*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v04E8pA100d0100dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0930p0A13d00*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0930p0A13d0100dc*dsc*dp*ic*isc*ip*in*

alias: usb:v17EFp304Bd00*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v17EFp304Bd0100dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0DF6p0072d00*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0DF6p0072d0100dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0B95p178Ad00*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0B95p178Ad0100dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0B95p1790d00*dc*dsc*dp*ic*isc*ip*in*

alias: usb:v0B95p1790d0100dc*dsc*dp*ic*isc*ip*in*

depends:

name: ax_usb_nic

vermagic: 6.6.40-rt51-xilinx-g2b7f6f70a62a-dirty SMP preempt_rt mod_unload modversions ARMv7 p2v8

parm: bctrl:RX Bulk Control (int)

parm: blwt:RX Bulk Timer Low (int)

parm: bhit:RX Bulk Timer High (int)

parm: bsize:RX Bulk Queue Size (int)

parm: bifg:RX Bulk Inter Frame Gap (int)

Some traffic through the interface seems to happen (but only in TX, not in RX):

4: eth1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000

link/ether 6c:6e:07:03:06:18 brd ff:ff:ff:ff:ff:ff

RX: bytes packets errors dropped missed mcast

0 0 0 0 0 0

TX: bytes packets errors dropped carrier collsns

656 8 0 0 0 0

Although most things seems to go right, I amb not able to test connectivity through a ping nor have the interface working to use it in linuxptp hardware timestamp (nor with software timestamps; while for the onboard Ethernet eth0 with software timestamps works).

root@AvnetMicroZedproj7010:~# ptp4l -i eth1

Floating point exception

Is the device tree settings correct? Is the driver correct? Is the standard Vivado design enough? Which way could I further investigate and debug the operation of this USB-ETH Device?

I modified system-user.dtsi as:

/include/ "system-conf.dtsi"

/ {

};

usb_phy0:phy0 {

compatible="ulpi-phy";

//compatible = "xlnx,zynq-usb-2.20.a", "chipidea,usb2";

phy_type = "ulpi"; // "ulpi" ?? "mii"

#phy-cells = <0>;

reg = <0xe0002000 0x1000>;

view-port=<0x170>;

drv-vbus;

};

&usb0 {

status = "okay";

dr_mode = "host";

usb-phy = <&usb_phy0>;

} ;

Microzed PMOD's inaccessible

TomerSh — Wed, 19 Mar 2025 07:38:09 GMT

Hello!
I am having some problems accessing MIO_13, MIO_12, MIO_11, MIO_10, which correspond to Pmod's D0-D3.
My system is built from a customized PCB with two DACs that is connected via J1-J2 to the Microzed board. I'm working with Vivado and Vitis v2022.1.
My Vivado design is a very simple zynq processor with the GPIO and some other peripherals enabled, I double-checked that the specific MIOs are GPIO:
in VIvado:

in Vitis:

I am using xspio_polled_example.c gpio example file (with some changes) in order to operate the LED in my board, and all PMODs. Upon running the program, MIO_0,9,14,15 as well as the LED on the board are responding, but the problematic MIOs are not.
I am connected via the PMOD interface:

some additional info:
I am working with Vitis because I encountered the same problem in Pynq and in the official linux image provided by microzed in their website, and wanted to be sure that my PS is configured right.

If anyone has an idea what could cause the problem, please share this information.

Thank you in advence, Tomer

Microzed Board Definition File (BDF) DDR Settings

padudle — Sun, 02 Mar 2025 16:16:50 GMT

Hello,

I am trying to use a Microzed board to demonstrate some ideas using the latest Vivado 2024.2 and Avnet-Tria BDF files. Unfortunately, I have not been able to get the DDR3 memory to run reliably.

First, I tried to boot Petalinux but operation was erratic. In most cases the board did not send any text to the console after pressing the reset button. I suspected the DDR3 memory so I built a Vitis bare metal application but I also found it to be very unreliable running from the DDR3 which is the default. Finally, I edited the linker script to put .data, .text and .bss in the Zynq On-Chip Memory (OCM). This boots and runs reliably.

Next, I looked at the DDR3 settings in the IP Integrator block diagram of my FPGA design. At a glance I can see that the memory size is not set correctly. The settings call out 2048Mb per chip while the chips are actually 256Mx16 = 4096Mb. In my Vitis project I can see it thinks the DDR3 is only 512MB in size. I have looked a the Microzed schematics, Rev H and Rev F, and they both have 1GB DDR3.

The DDR3 settings in my FPGA project come from the Avnet BDF file for the Microblaze. I am using https://github.com/Avnet/bdf/tree/master/microzed_7020/1.4.

I think this means there are errors in the Microblaze BDF that prevent correct operation.

AXI GPIO PL

Maxzed — Thu, 13 Feb 2025 15:40:04 GMT

Dear all,

This is my first post, so please be patient if I make any mistakes.

I am working with a MicroZed board, using Vivado 2024 and PetaLinux 2024. I am following some tutorials to create a simple project with:

Zynq processor
AXI GPIO

Goal:

I want to control a GPIO on JX2 of the MicroZed.

The specific pin is pin 13 on JX2, which corresponds to G14 on bank 35.

My XDC file:

set_property PACKAGE_PIN G14 [get_ports gpio_io_o_0[0]]
set_property IOSTANDARD LVCMOS33 [get_ports gpio_io_o_0[0]]

I created my Vivado project, assigned an address to the AXI GPIO interface, and built my PetaLinux project. I then booted the MicroZed using an SD card.

Everything seems to work correctly. Running the following command:

ls -lh /sys/class/gpio

I get:

--w------- 1 root root 4.0K Jan 1 1970 export
lrwxrwxrwx 1 root root 0 Jan 1 1970 gpiochip512 -> ../../devices/soc0/pl-bus/41200000.gpio/gpio/gpiochip512
lrwxrwxrwx 1 root root 0 Jan 1 1970 gpiochip515 -> ../../devices/soc0/axi/e000a000.gpio/gpio/gpiochip515
--w------- 1 root root 4.0K Jan 1 1970 unexport

This confirms that gpiochip512 is correctly mapped to my PL AXI GPIO.

I also added an ILA (Integrated Logic Analyzer) in my PL design. When I toggle the GPIO with:

echo 1 > /sys/class/gpio/gpio512/value

I can see the GPIO signal changing in the ILA.

Issue:

However, when I check the physical pin (JX2, pin 13) with an oscilloscope, I see no signal change.

Has anyone encountered a similar issue? Any suggestions on what I might be missing?

Thanks in advance for your help!

Is there a mz7010_som_base_2024_1.bsp file?

Andy-75 — Fri, 15 Nov 2024 14:53:14 GMT

I can find one for 2023_2 but not 2024. I am working on a new project starting with the microZed and wanted to use the latest PetaLinux tools.

I found the 2023 version here but it does not have a microZed for 2024.

avtinc.sharepoint.com/.../AllItems.aspx

MicroZed IO Carrier Card design files

emazzola — Thu, 18 Jul 2024 11:48:27 GMT

Is there any way to access the design files for the AES-MBCC-IO-G?

Can't program the Microzed 7020. Tried different versions of Vivado

kpham — Fri, 21 Jun 2024 13:38:29 GMT

Hello,

I have a Microzed 7020 board, and I've been trying to program it in JTAG boot mode, but the board doesn't seem to work. I've been following different tutorials online, and always got stuck at the basic printing Hello World program. Namely, when I run the program, Vitis recognizes the board, and the board's blue LED (done LED) is turned on, but nothing seems to show up on Vitis serial terminal or Tera Term (both are tried individually to make sure there's no clashing of the terminals). When I tried using the xgpio examples that come with the BSP settings, the LEDs aren't responsive as well.

The board does work when I program the FPGA side (using pure verilog and flashing from Vivado), and does have a linux interface showing up when I use the QSPI boot mode, i.e., the USB-UART port seems to work.

The only thing that doesn't seem to work is flashing the code from Vitis to program the non-FPGA side of the processor.

This problem has been tried with different versions of Vivado/Vitis (2024, 2023, 2023, 2015), and the problem persists.

Thanks in advance!

Microzed Connection Issue

kpham — Mon, 10 Jun 2024 17:52:08 GMT

Hello,

I have just started using the Microzed 7020, and I've been trying to flash some example code on to the board, but I keep having this error when using Vitis 2024.1:

The error message is:

"Could not find ARM device on the board for connection 'Local'. Check if the target is in:

Split JTAG - No operations are possible with ARM DAP.
Non JTAG bootmode - Bootrom may need time to enable DAP.

Please try again. Troubleshooting hints:

Check whether board is connected to system properly.
In case of zynq board, check whether Digilent/Xilinx cable switch settings are correct.
If you are using Xilinx Platform Cable USB, ensure that status LED is green"

Tera Term seems to be able to recognize the COM port and the connection, but nothing is showing up on the terminal as well.

When I use Vivado 2024.1's hardware manager, it also doesn't seem to be able to connect to the board.

I've tried updating the drivers, but nothing works.

Could someone please point me in the right direction? Thank you very much.

cannot find -l-Wl,--start-group,-lxil,-lfreertos,-lgcc,-lc,--end-group: No such file or directory

quadzilla — Thu, 06 Jun 2024 14:08:13 GMT

I've been getting this error. I have no idea what it means or how to fix it. Can anyone help?

Microzed 7Z010 rev H having intermittent Ethernet issues

ebconcannon — Fri, 03 May 2024 02:01:15 GMT

Microzed 7010 rev H having intermittent Ethernet issues on boot. Happens when cold or hot. Occurs on 2 of latest batch of 300 boards. Has anyone seen this before?

How to red DDR vs BRAM

quadzilla — Wed, 06 Mar 2024 14:56:24 GMT

This is another doubtlessly naive question. I know that you can read the BRAM by using XBram_ReadReg() and a BRAM controller. Also that XBram_ReadReg() basically amounts to using Xil_In32() to read a memory location.

Can we do something similar to read the DDR RAM, or are we always forced to use the routines in xaxidma_bdring.c?

Vitis stalls when trying to create platform component

quadzilla — Fri, 16 Feb 2024 21:21:28 GMT

I'm trying to use non-classic Vitis 2023.2 to create a platform component, but it keep stalling after I select an XSA file. The little status circle after "Creating System Device Tree from the XSA and getting processor details keeps spinning ad infinitum."

Any tips on how to proceed? I tried to follow a couple of online guides for downloading and debugging the device tree generator, but I keep getting an error when I try to clone GitHub - Xilinx/system-device-tree-xlnx

No clock or GPIO displayed for MicroZed board?

quadzilla — Fri, 09 Feb 2024 16:41:19 GMT

I've been trying to create a Vivado project for the MicroZed 7020 board. While fumbling through some online tutorials, I noticed that after I select this board type (file version 1.3) here aren't any clock or GPIO components listed under the board tab.

Is this normal? I'm trying to figure out if there might be something wrong with my Vivado setup.

I found the same problem when I specify a MicroZed 7010 instead but not other board types.

Gerber files for the MicroZed

jvlesage — Wed, 07 Feb 2024 16:19:39 GMT

Are Greber files available for any recent versions for the MicroZed? I'd like to take a look at the DDR3 layout.

Documentation on Microzed SBC (Upper Side Connectors)

vcasado31 — Mon, 05 Feb 2024 23:06:09 GMT

Hello,

I have a Microzed with Zynq 7020 and the Micromod connectors in the top side. I have build a Petalinux image, and the FPGA Done blue LED lights up, but I cannot connect with the board trohugh any terminal (SSH/Serial).

I have looked for info, but I just got searching for Microzed SBC this following doc PB-AES-Z7MB-7Z010_20-SBC-G-V1, but no schematics/references...

Does anyone can ping me some short of documentation about this board, please?

Thank you!

MicroZed Board Defs and Vivado versions.

abalducci — Sat, 27 Jan 2024 12:57:12 GMT

Hi, so I have a MicroZed BD-Z7MB-7201-G RevF6. I've had this board for awhile for it, just not had a chance to play with it. I know this is somewhat of an older product, but on the support site I notice board def files are only listed up to Vivado 2017. Is it still recommended to use one of these older versions or is there a chance they'd work with more recent versions as well?

MicroZed AES-Z7MB-7Z020-SOM-I-G

2shahni — Fri, 26 Jan 2024 00:32:06 GMT

Hello. We currently buy MicroZed AES-Z7MB-7Z020-SOM-I-G from you guys. We track vendor S/N from you in our database. Wanted to confirm if we are capturing this correctly. Currently we only log the last six digits. My assumption is you want the full 21 digits. Please see attached pictures below.

Pic 1 & 2 are the same but pic 3, the s/n on the board is in a different order.

If you can please clarify which s/n to use, that would be greatly appreciated!

Can anyone provide a simple, almost blank project?

quadzilla — Thu, 25 Jan 2024 20:10:45 GMT

My team could use some help. Would someone be so kind as to provide a simple, nearly empty Vitis 2023 project for the MicroZed? We're having some trouble getting started and the Avnet tutorials are out of date. Trying to figure out why my projects don't execute.