MicroZed Hardware Design - Recent Threads

Microzed 7020 Device Tree

dwoods105 — Thu, 30 Oct 2025 21:39:27 GMT

Hello,

I have a 7020 Microzed. I am currently building the image with Yocto with the Gen-Machine-Conf Parse-SDT workflow from AMD.

I am attempting to get the USB PHY to work. I would like to to be in peripherial mode, but I can't get it working at all.

Gen-Machine-conf gives me the standard device tree files, and I am using a custom DTSI that is included in the system-top.

Does anyone know what I'm doing wrong?[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:f6aa0885-527e-483b-8d5d-1c2b02b8a36a:type=text&text=%2Fdts-v1%2F%3B%0D%0A%23include%20%22zynq-7000.dtsi%22%0D%0A%23include%20%22pl.dtsi%22%0D%0A%23include%20%22pcw.dtsi%22%0D%0A%2F%20%7B%0D%0A%09device_id%20%3D%20%227z020%22%3B%0D%0A%09slrcount%20%3D%20%3C1%3E%3B%0D%0A%09family%20%3D%20%22Zynq%22%3B%0D%0A%09speed_grade%20%3D%20%221%22%3B%0D%0A%09VIPER_FPGA_PIXBUF_memory%3A%20memory%4040000000%20%7B%0D%0A%09%09compatible%20%3D%20%22xlnx%2Caxi-bram-ctrl-4.1%22%3B%0D%0A%09%09xlnx%2Cip-name%20%3D%20%22axi_bram_ctrl%22%3B%0D%0A%09%09device_type%20%3D%20%22memory%22%3B%0D%0A%09%09memory_type%20%3D%20%22memory%22%3B%0D%0A%09%09reg%20%3D%20%3C0x40000000%200x200000%3E%3B%0D%0A%09%7D%3B%0D%0A%09VIPER_FPGA_REGS_memory%3A%20memory%4080000000%20%7B%0D%0A%09%09compatible%20%3D%20%22xlnx%2Caxi-bram-ctrl-4.1%22%3B%0D%0A%09%09xlnx%2Cip-name%20%3D%20%22axi_bram_ctrl%22%3B%0D%0A%09%09device_type%20%3D%20%22memory%22%3B%0D%0A%09%09memory_type%20%3D%20%22memory%22%3B%0D%0A%09%09reg%20%3D%20%3C0x80000000%200x80000%3E%3B%0D%0A%09%7D%3B%0D%0A%09ps7_qspi_linear_0_memory%3A%20memory%40fc000000%20%7B%0D%0A%09%09compatible%20%3D%20%22xlnx%2Cps7-qspi-linear-1.00.a-memory%22%3B%0D%0A%09%09xlnx%2Cip-name%20%3D%20%22ps7_qspi_linear%22%3B%0D%0A%09%09device_type%20%3D%20%22memory%22%3B%0D%0A%09%09memory_type%20%3D%20%22linear_flash%22%3B%0D%0A%09%09reg%20%3D%20%3C0xfc000000%200x1000000%3E%3B%0D%0A%09%7D%3B%0D%0A%09ps7_ddr_0_memory%3A%20memory%4000100000%20%7B%0D%0A%09%09compatible%20%3D%20%22xlnx%2Cps7-ddr-1.00.a%22%3B%0D%0A%09%09xlnx%2Cip-name%20%3D%20%22ps7_ddr%22%3B%0D%0A%09%09device_type%20%3D%20%22memory%22%3B%0D%0A%09%09memory_type%20%3D%20%22memory%22%3B%0D%0A%09%09reg%20%3D%20%3C0x00100000%200x3FF00000%3E%3B%0D%0A%09%7D%3B%0D%0A%09ps7_ram_0_memory%3A%20memory%400%20%7B%0D%0A%09%09compatible%20%3D%20%22xlnx%2Cps7-ram-1.00.a%22%3B%0D%0A%09%09xlnx%2Cip-name%20%3D%20%22ps7_ram%22%3B%0D%0A%09%09device_type%20%3D%20%22memory%22%3B%0D%0A%09%09memory_type%20%3D%20%22memory%22%3B%0D%0A%09%09reg%20%3D%20%3C0x0%200x30000%3E%3B%0D%0A%09%7D%3B%0D%0A%09ps7_ram_1_memory%3A%20memory%40ffff0000%20%7B%0D%0A%09%09compatible%20%3D%20%22xlnx%2Cps7-ram-1.00.a%22%3B%0D%0A%09%09xlnx%2Cip-name%20%3D%20%22ps7_ram%22%3B%0D%0A%09%09device_type%20%3D%20%22memory%22%3B%0D%0A%09%09memory_type%20%3D%20%22memory%22%3B%0D%0A%09%09reg%20%3D%20%3C0xffff0000%200xfe00%3E%3B%0D%0A%09%7D%3B%0D%0A%09chosen%20%7B%0D%0A%09%09stdout-path%20%3D%20%22serial0%3A115200n8%22%3B%0D%0A%09%7D%3B%0D%0A%09aliases%20%7B%0D%0A%09%09serial0%20%3D%20%26uart1%3B%0D%0A%09%09spi0%20%3D%20%26qspi%3B%0D%0A%09%09serial1%20%3D%20%26coresight%3B%0D%0A%09%09spi1%20%3D%20%26VIPER_TRIGDAC_SPI%3B%0D%0A%09%09spi2%20%3D%20%26VIPER_ADC_SPI%3B%0D%0A%09%09ethernet0%20%3D%20%26gem0%3B%0D%0A%09%7D%3B%0D%0A%09cpus_a9%3A%20cpus-a9%400%20%7B%0D%0A%09%09compatible%20%3D%20%22cpus%2Ccluster%22%3B%0D%0A%09%09address-map%20%3D%20%3C0xf0000000%20%26amba%200xf0000000%200x10000000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x40000000%20%26VIPER_FPGA_PIXBUF_memory%200x40000000%200x200000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x40000000%20%26VIPER_FPGA_PIXBUF%200x40000000%200x200000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x80000000%20%26VIPER_FPGA_REGS_memory%200x80000000%200x80000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x80000000%20%26VIPER_FPGA_REGS%200x80000000%200x80000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x00100000%20%26ps7_ddr_0_memory%200x00100000%200x3FF00000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x0%20%26ps7_ram_0_memory%200x0%200x30000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xffff0000%20%26ps7_ram_1_memory%200xffff0000%200xfe00%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x40200000%20%26axi_gpio_0%200x40200000%200x10000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x81e00000%20%26VIPER_ADC_SPI%200x81e00000%200x10000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x81e10000%20%26VIPER_TRIGDAC_SPI%200x81e10000%200x10000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0x83c00000%20%26axi_xadc_0%200x83c00000%200x10000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xf8008000%20%26ps7_afi_0%200xf8008000%200x1000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xf8009000%20%26ps7_afi_1%200xf8009000%200x1000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xf800a000%20%26ps7_afi_2%200xf800a000%200x1000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xf800b000%20%26ps7_afi_3%200xf800b000%200x1000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xf8800000%20%26coresight%200xf8800000%200x100000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xf8006000%20%26mc%200xf8006000%200x1000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xf8007000%20%26devcfg%200xf8007000%200x100%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xf8004000%20%26ps7_dma_ns%200xf8004000%200x1000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xf8003000%20%26dmac_s%200xf8003000%200x1000%3E%2C%20%0D%0A%09%09%09%20%20%20%20%20%20%3C0xe000b000%20%26gem0%200xe000b000%200x1000%3E%2C%20%0D%0A%09%09%09%20%20%20%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Thanks in advance![embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:4a233944-7e25-409c-aec3-59f4f1865f42:type=text&text=%2F%2F%20SPDX-License-Identifier%3A%20GPL-2.0%0D%0A%2F%2A%0D%0A%20%2A%20USB%20peripheral%20fix%20for%20Avnet%20MicroZed%20%28Zynq-7000%29%0D%0A%20%2A%20Keeps%20baseline%20bootability%20while%20correcting%20ULPI%20PHY%20definition.%0D%0A%20%2A%2F%0D%0A%0D%0A%20%2Finclude%2F%20%22zynq-7000.dtsi%22%0D%0A%0D%0A%2F%20%7B%0D%0A%09model%20%3D%20%22Avnet%20MicroZed%20board%22%3B%0D%0A%09compatible%20%3D%20%22avnet%2Czynq-microzed%22%2C%20%22xlnx%2Czynq-microzed%22%2C%20%22xlnx%2Czynq-7000%22%3B%0D%0A%0D%0A%09amba%3A%20amba%20%7B%0D%0A%09%09usb0%3A%20usb%40e0002000%20%7B%0D%0A%09%09%09compatible%20%3D%20%22xlnx%2Czynq-usb-2.20a%22%2C%20%22chipidea%2Cusb2%22%3B%0D%0A%09%09%09reg%20%3D%20%3C0xe0002000%200x1000%3E%3B%0D%0A%09%09%09interrupt-parent%20%3D%20%3C%26intc%3E%3B%0D%0A%09%09%09interrupts%20%3D%20%3C0%2021%204%3E%3B%0D%0A%09%09%09clocks%20%3D%20%3C%26clkc%2028%3E%3B%0D%0A%09%09%09dr_mode%20%3D%20%22peripheral%22%3B%0D%0A%09%09%09usb-phy%20%3D%20%3C%26usb_phy0%3E%3B%0D%0A%09%09%09status%20%3D%20%22okay%22%3B%0D%0A%09%09%7D%3B%0D%0A%0D%0A%09%09usb_phy0%3A%20phy0%20%7B%0D%0A%09%09%09compatible%20%3D%20%22ulpi-phy%22%3B%0D%0A%09%09%09%23phy-cells%20%3D%20%3C0%3E%3B%0D%0A%09%09%09view-port%20%3D%20%3C0x170%3E%3B%0D%0A%09%09%09drv-vbus%3B%0D%0A%09%09%7D%3B%0D%0A%09%7D%3B%0D%0A%0D%0A%09aliases%20%7B%0D%0A%09%09ethernet0%20%3D%20%26gem0%3B%0D%0A%09%09serial0%20%3D%20%26uart1%3B%0D%0A%09%7D%3B%0D%0A%0D%0A%09memory%400%20%7B%0D%0A%09%09device_type%20%3D%20%22memory%22%3B%0D%0A%09%09reg%20%3D%20%3C0x0%200x40000000%3E%3B%0D%0A%09%7D%3B%0D%0A%0D%0A%09chosen%20%7B%0D%0A%09%09bootargs%20%3D%20%22earlycon%22%3B%0D%0A%09%09stdout-path%20%3D%20%22serial0%3A115200n8%22%3B%0D%0A%09%7D%3B%0D%0A%7D%3B%0D%0A%0D%0A%26clkc%20%7B%0D%0A%09ps-clk-frequency%20%3D%20%3C33333333%3E%3B%0D%0A%7D%3B%0D%0A%0D%0A%26gem0%20%7B%0D%0A%09status%20%3D%20%22okay%22%3B%0D%0A%09phy-mode%20%3D%20%22rgmii-id%22%3B%0D%0A%09phy-handle%20%3D%20%3C%26ethernet_phy%3E%3B%0D%0A%0D%0A%09ethernet_phy%3A%20ethernet-phy%400%20%7B%0D%0A%09%09reg%20%3D%20%3C0%3E%3B%0D%0A%09%7D%3B%0D%0A%7D%3B%0D%0A%0D%0A%26sdhci0%20%7B%0D%0A%09status%20%3D%20%22okay%22%3B%0D%0A%7D%3B%0D%0A%0D%0A%26uart1%20%7B%0D%0A%09status%20%3D%20%22okay%22%3B%0D%0A%7D%3B%0D%0A]

RE: Microzed 7020 Device Tree

dwoods105 — Mon, 17 Nov 2025 14:46:45 GMT

The issue is solved. The reset pin for the USB-PHY wasn't enabled in Vivado. It was an issue with the bitstream

RE: Microzed 7020 Device Tree

iksevas — Tue, 04 Nov 2025 15:45:31 GMT

Here is some other information from users targeting USB on MicroZed.

(+) Microzed USB configuration for petalinux 2018 - element14 Community

RE: Microzed 7020 Device Tree

dwoods105 — Tue, 04 Nov 2025 14:49:28 GMT

Doesn't this line instantiate a dummy phy?

compatible="usb-nop-xceiv";

On line 44. I am relatively new at this.

RE: Microzed 7020 Device Tree

iksevas — Tue, 04 Nov 2025 00:02:06 GMT

petalinux/configs/device-tree/system-user.dtsi.mz_petalinux at 2017.4 · Avnet/petalinux

This is a device tree for the MicroZed on 2017.4 posted to Avnet GITHUB.

How to perform DDR3 PCB layout for Xilinx FPGA, MicroZed provides any layout/gerber files?

rajhlinux — Tue, 15 Jul 2025 04:20:25 GMT

Any PCB Layout/gerber files for MicroZed, so that I can get a good understanding in laying out the DDR3 traces on PCB? My goal is to learn how to layout DDR3 traces to an FPGA, I can't find any sources that teaches in detailed in how to do so and reading just a text document such as design reference documentation is not too helpful.

I found this link which contains a PDF of "Mechanical drawings" for MicroZed:

https://www.avnet.com/americas/products/avnet-boards/avnet-board-families/microzed/

https://www.avnet.com/wcm/connect/2908a4d7-4434-49ca-b37d-661551898d68/PRJ-US2SOM-1-01-03-PDF3D.PDF?MOD=AJPERES&CACHEID=ROOTWORKSPACE-2908a4d7-4434-49ca-b37d-661551898d68-nDjeMQQ

However, the CAD file being rendered in PDF format, seems to be for a different board other than MicroZed board. The CAD PDF file only works with Acrobat Reader and is super slow to render (I have a beefy NVIDIA RTX 3080 TI GPU).

It is extremely tricky to view the layers. Any guide in how to properly operate this CAD PDF file to view the DDR3 PCB traces?

Thanks for any info.

Ethernet PHY problems on MicroZed rev. H

rgaddi — Tue, 17 Jun 2025 16:43:06 GMT

I'm having intermittent problems communicating with the Marvell Ethernet PHY on the MicroZed. Very possibly the same problem as Microzed 7Z010 rev H having intermittent Ethernet issues a year ago.

According to the system message log, and confirming with mii-diag and phy-tool, it looks like it's failing to find the PHY. My hunch is that it's a continuation of the same reset problem seen on previous MicroZed revisions.

If I It will usually identify the PHY correctly and communicate with it from a very cold boot, like it's been off for half an hour cold boot. And will often keep finding it through several power cycles after that. But at some point it'll stop finding the PHY, and one it does the PHY is lost for however many more quick power cycles. But then if I get a grounded wire and hold PG_MODULE low externally (which is the only thing on the board that triggers a PHY reset) then all of a sudden the PHY works and keeps working.

I've got the MicroZed connected to a custom carrier; that carrier only monitors PG_MODULE and does not drive it.

Some units with this intermittent failure went into the field, and are now failing intermittently at customer sites, so we've got a real problem. I have no way of identifying which MicroZeds will and will not show the problem because again, it's intermittent. So my not having seen a given unit fail yet means nothing.

RE: Ethernet PHY problems on MicroZed rev. H

rgaddi — Tue, 24 Jun 2025 19:01:12 GMT

Can't find anything digging through the driver code. Tried using devmem to force an MDIO reset by writing the XEMACPS_PHYMNTNC register, but no luck.

What does seem to work, lending more credence to the idea that the Microzed reset logic is too touchy, is that I added an STM1818 power-on-reset chip. It's monitoring my carrier's VCCO supply to the zed, and using that (as well as monitoring PG_MODULE) to ensure a minimum 100ms reset on PG_MODULE. For a Microzed that I was able to get to consistently fail, with the POR chip in it seems to consistently succeed.

Having to jury-rig this onto existing units and eventually spin my board to cover this is going to be brutal though.

RE: Ethernet PHY problems on MicroZed rev. H

iksevas — Tue, 24 Jun 2025 04:31:48 GMT

RE: Ethernet PHY problems on MicroZed rev. H

rgaddi — Tue, 24 Jun 2025 00:36:45 GMT

Thanks. I took a look across the level-shifter and the 1.8V side follows the 3.3V side cleanly and quickly.

On at least one Microzed so far the problem seems to be linked to whether the Ethernet cable is connected; with the cable disconnected the PHY can be found just fine (and will then proceed to work), but with the cable connected to the network it loses the PHY.

Software reset over MDIO would be tempting, but I can't find a way to force one. Whether or not the PHY has been detected I get

# ethtool --reset eth0 all
ETHTOOL_RESET 0xffffffff
Cannot issue ETHTOOL_RESET: Operation not supported

phytool just gives me error -22 about everything, and as far as I can tell doesn't even attempt to clock anything out the MDIO.

Other things I've found:

There's a blip on the ETH_RST_N line (output of the last AND gate that drives the PHY) on power up during the sequence prior to the actual reset generation.
Because the TXS0102 only pulls up the output ETH_RST_# with 10k, the RC time-constant in the pull-up direction is about 3x what you'd expect from the datasheet.
The PHY apparently once-upon-a-time had an errata sheet, but either it's no longer available or I'd need a Marvell NDA to even be allowed to know such a thing exists. But there was once such a thing, and in 2014 led to some changes to the driver under both Linux and U-Boot to handle some behavior on reboot.

RE: Ethernet PHY problems on MicroZed rev. H

iksevas — Mon, 23 Jun 2025 22:32:12 GMT

There is an RC circuit in the way. Perhaps the way you are cycling isn’t allowing the PG module signal or the cap in the RC to discharge enough to reset the PHY?

There probably should be a path to GND there to discharge those signals through.

If i were you l, I would put a scope on the PG module signal (input) and the translator (output) and review the behavior.

Another option would be SW reset if possible using MDIO interface.

RE: Ethernet PHY problems on MicroZed rev. H

rgaddi — Mon, 23 Jun 2025 17:12:48 GMT

On the chance this was some kind of a configuration issue on my end I tried firing up the baseline image available at "Open Source Linux boot images for MicroZed 7010/7020". After a couple of reboots I get the same problem; a dead Ethernet link that, when I go in and ask over the serial console, shows me in dmesg


root@zynq:~# dmesg | grep ethernet
xemacps e000b000.ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
xemacps e000b000.ethernet: eth0: no PHY found
xemacps e000b000.ethernet: XEMACPS mii bus mii_probe fail.

Following this test, to confirm that the problem is not with the way we're powering or resetting the Microzed, I removed it from our custom carrier board and, just powering through the USB cable and unplugging it for roughly 1 second before plugging it back in, was able to once again replicate the behavior. No PHY found.

MicroZed PetaLinux 2023.2 spidev transfer timed out

acountryman25 — Mon, 19 May 2025 19:53:47 GMT

This question has also been posted to the AMD Adaptive Support forums (https://adaptivesupport.amd.com/s/question/0D5KZ00000pAdsk0AC/zynq-7000-petalinux-20232-spidev-transfer-timed-out).

The team I am a member of is currently working on upgrading a project we inherited from the 2014 tools (Vivado, PetaLinux, etc) to the 2023.2 tools. This project uses PetaLinux running on an Avnet MicroZed AES-Z7MB-7Z020-SOM-G (XC7Z020-1CLG400C). We have encountered an issue with SPI 1 that we have not been able to resolve ("spidev spi1.X: SPI transfer timed out", "spi_master spi1: failed to transfer one message from queue", the state of the SPI 1 pins/signals has been checked and they are in their idle state with no activity observed).

The PetaLinux 2023.2 project was created using the scripts/make_mz7020_som_base.sh script from the Avnet petalinux GitHub repository's 2023.2 branch. The following changes have been made to the petalinux and meta-avnet repositories:

Made various modifications so that the build can be performed without internet access.
Made the following build configuration changes:
- Changed BOOT_METHOD to INITRD
- Set BOOT_SUFFIX to _MINIMAL
- Set INITRAMFS_IMAGE to petalinux-image-minimal
Removed axi_intc_0 and amba_pl entries from meta-avnet/recipes-bsp/device-tree/files/mz/system-bsp.dtsi to fix rebuild errors that occur when the XSA file is swapped out for the one from our Vivado project.

SPI transfers are done using SPI_IOC_MESSAGE ioctl() calls.

SPI 1 is configured as follows in Vivado:

SPI 1 is enabled and is configured to use MIO 10 .. 15
- MIO 10:
  - Signal: mosi
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: disabled
  - Direction: inout
- MIO 11:
  - Signal: miso
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: enabled
  - Direction: inout
- MIO 12:
  - Signal: sclk
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: disabled
  - Direction: inout
- MIO 13:
  - Signal: ss[0]
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: enabled
  - Direction: inout
- MIO 14:
  - Signal: ss[1]
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: enabled
  - Direction: out
- MIO 15:
  - Signal: ss[2]
  - IO Type: LVCMOS 3.3V
  - Speed: slow
  - Pullup: enabled
  - Direction: out

dtsi SPI 1 configuration overrides:

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:fa9dd6dc-d235-4156-9c76-9636e826ea10:type=text&text=%26spi1%20%7B%0A%20%20%20%20status%20%3D%20%22okay%22%3B%0A%20%20%20%20num-cs%20%3D%20%3C3%3E%3B%0A%20%20%20%20is-decoded-cs%20%3D%20%3C0%3E%3B%0A%20%20%20%20speed-hz%3D%3C10000000%3E%3B%0A%20%0A%20%20%20%20device%400%7B%0A%20%20%20%20%20%20%20%20status%20%3D%20%22okay%22%3B%0A%20%20%20%20%20%20%20%20compatible%3D%22rohm%2Cdh2228fv%22%3B%20%20%20%2F%2F%20Not%20actually%20this%20device%2C%20workaround%20to%20get%20%2Fdev%2Fspidev1.0%20to%20appear.%0A%20%20%20%20%20%20%20%20reg%3D%3C0%3E%3B%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%2F%2F%20Chipselect%200%0A%20%20%20%20%20%20%20%20spi-max-frequency%3D%3C10000000%3E%3B%20%2F%2F%2010%20Mhz%0A%20%20%20%20%7D%3B%0A%20%0A%20%20%20%20device%401%7B%0A%20%20%20%20%20%20%20%20status%20%3D%20%22okay%22%3B%0A%20%20%20%20%20%20%20%20compatible%3D%22rohm%2Cdh2228fv%22%3B%20%20%20%2F%2F%20Not%20actually%20this%20device%2C%20workaround%20to%20get%20%2Fdev%2Fspidev1.0%20to%20appear.%0A%20%20%20%20%20%20%20%20reg%3D%3C1%3E%3B%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%2F%2F%20Chipselect%201%0A%20%20%20%20%20%20%20%20spi-max-frequency%3D%3C10000000%3E%3B%20%2F%2F%2010%20Mhz%0A%20%20%20%20%7D%3B%0A%20%0A%20%20%20%20device%402%7B%0A%20%20%20%20%20%20%20%20status%20%3D%20%22okay%22%3B%0A%20%20%20%20%20%20%20%20compatible%3D%22rohm%2Cdh2228fv%22%3B%20%20%20%2F%2F%20Not%20actually%20this%20device%2C%20workaround%20to%20get%20%2Fdev%2Fspidev1.0%20to%20appear.%0A%20%20%20%20%20%20%20%20reg%3D%3C2%3E%3B%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%20%2F%2F%20Chipselect%202%0A%20%20%20%20%20%20%20%20spi-max-frequency%3D%3C10000000%3E%3B%20%2F%2F%2010%20Mhz%0A%20%20%20%20%7D%3B%0A%7D%3B]

SPI 1 device tree entry from decompiled DTB:

[embed:dc8ab71f-3b98-42d9-b0f6-e21e02a0f8e2:af2cbb4d-0634-45a4-937e-c3add5b47709:type=text&text=spi%40e0007000%20%7B%0D%0A%20%20%20%20compatible%20%3D%20%22xlnx%2Czynq-spi-r1p6%22%3B%0D%0A%20%20%20%20reg%20%3D%20%3C0xe0007000%200x1000%3E%3B%0D%0A%20%20%20%20status%20%3D%20%22okay%22%3B%0D%0A%20%20%20%20interrupt-parent%20%3D%20%3C0x04%3E%3B%0D%0A%20%20%20%20interrupts%20%3D%20%3C0x00%200x31%200x04%3E%3B%0D%0A%20%20%20%20clocks%20%3D%20%3C0x01%200x1a%200x01%200x23%3E%3B%0D%0A%20%20%20%20clock-names%20%3D%20%22ref_clk%5C0pclk%22%3B%0D%0A%20%20%20%20%23address-cells%20%3D%20%3C0x01%3E%3B%0D%0A%20%20%20%20%23size-cells%20%3D%20%3C0x00%3E%3B%0D%0A%20%20%20%20num-cs%20%3D%20%3C0x03%3E%3B%0D%0A%20%20%20%20is-decoded-cs%20%3D%20%3C0x00%3E%3B%0D%0A%20%20%20%20speed-hz%20%3D%20%3C0x989680%3E%3B%0D%0A%20%20%20%20phandle%20%3D%20%3C0x24%3E%3B%0D%0A%20%0D%0A%20%20%20%20device%400%20%7B%0D%0A%20%20%20%20%20%20%20%20status%20%3D%20%22okay%22%3B%0D%0A%20%20%20%20%20%20%20%20compatible%20%3D%20%22rohm%2Cdh2228fv%22%3B%0D%0A%20%20%20%20%20%20%20%20reg%20%3D%20%3C0x00%3E%3B%0D%0A%20%20%20%20%20%20%20%20spi-max-frequency%20%3D%20%3C0x989680%3E%3B%0D%0A%20%20%20%20%7D%3B%0D%0A%20%0D%0A%20%20%20%20device%401%20%7B%0D%0A%20%20%20%20%20%20%20%20status%20%3D%20%22okay%22%3B%0D%0A%20%20%20%20%20%20%20%20compatible%20%3D%20%22rohm%2Cdh2228fv%22%3B%0D%0A%20%20%20%20%20%20%20%20reg%20%3D%20%3C0x01%3E%3B%0D%0A%20%20%20%20%20%20%20%20spi-max-frequency%20%3D%20%3C0x989680%3E%3B%0D%0A%20%20%20%20%7D%3B%0D%0A%20%0D%0A%20%20%20%20device%402%20%7B%0D%0A%20%20%20%20%20%20%20%20status%20%3D%20%22okay%22%3B%0D%0A%20%20%20%20%20%20%20%20compatible%20%3D%20%22rohm%2Cdh2228fv%22%3B%0D%0A%20%20%20%20%20%20%20%20reg%20%3D%20%3C0x02%3E%3B%0D%0A%20%20%20%20%20%20%20%20spi-max-frequency%20%3D%20%3C0x989680%3E%3B%0D%0A%20%20%20%20%7D%3B%0D%0A%7D%3B]

We have tried the following to resolve this issue but they were not successful:

Disabling power management in the kernel configuration as suggested by some adaptivesupport posts
Increasing the timeout period as was done for https://adaptivesupport.amd.com/s/article/2021-Zynq-7000-Zynq-MPSoC-Versal-Yocto-PetaLinux-kernel-driver-fails-to-configure?language=en_US
Changing the SPI 1 interrupts configuration (<0 49 4>) to the configuration that was used in the old device tree (<0 49 0>)

Any suggestions for resolving this issue would be greatly appreciated.

Avnet MicroZed Product Compliance

DarrylPonting — Thu, 24 Apr 2025 10:08:45 GMT

Hello

I have been directed to these forums by Avnet to ask about Product compliance. I am trying to determine the RoHS and REACH compliance of the MicroZed, specifically AES-Z7MB-7Z020-SOM-I-G Rev H. I can see the RoHS compliance is quite clear, however everywhere seems to list REACH as TBA.

Hopefully someone here can help.

Thanks

RE: Avnet MicroZed Product Compliance

DarrylPonting — Fri, 25 Apr 2025 07:57:15 GMT

Thanks, I have just got in touch.

RE: Avnet MicroZed Product Compliance

iksevas — Thu, 24 Apr 2025 15:48:23 GMT

Sorry about the round about, but compliance information isn’t readily available on the forums. Send an email to customize@avnet.com.

I would be specific in the title of the email.

RE: Where to start: MicroZed 7020, Vivado 2024.2, Ubuntu 24.04

padudle — Sun, 13 Apr 2025 12:18:20 GMT

Running something simple in the FPGA fabric is a good place to start. It is nice to not mess with IO and the Microzed has no PL LEDs. I recommend an ILA core that is created in the IP Core Generator just like any other Xilinx core. It will terminate the outputs of any logic you have so that the synthesizer does not remove it from the design. You can then observe the behavior of your logic use the Hardware Manager feature of Vivado.

I like to do a lot of design verification in hardware, so I sprinkle ILA cores around as I write my code and then comment them out when I don't need them. Instantiation looks something like this.

logic [15:0] count=0, prod;

always_ff @(posedge clk) count <= count + 1;

assign prod = count * 3;

counter_ila counter_ila_inst (.clk(clk), .probe0({count, prod})); // 32 bits

I don't think Microzed has a dedicated oscillator into the PL so you will need to create a minimal CPU design in the IP Integrator. If you plunk down a CPU core in there, IPI will offer some automations to configure and wire it up in a valid way. Then you can bring out the CPU clock to run your PL design.

Where to start: MicroZed 7020, Vivado 2024.2, Ubuntu 24.04

eNtropy618 — Sat, 05 Apr 2025 17:47:29 GMT

Hello,

Can someone please point me in the right direction for getting started developing for the PS and PL using systemverilog & verilog, using Vivado 2024.2 on Ubuntu 24.04? I haven't touched an FPGA in 10 years, and I'm hoping this board is still supported. Some of the documentation I found so far points to dead links for support or reference. I was able to get Vivado installed following the instructions found at https://gist.github.com/aitesam961/51a8dd9b785d0cc9f0bed5faf51e982e, using whatever free amd/xilinx license came with the Vivado local installer. I have a small "JTAG-HS3 Rev. A" board that I'm using to interface with the Zynq board (note: I only have the small dev board, not the expansion board that it plugs into to expose all pins to the user's possible different use cases). When I connect it via USB to my computer, and connect another usb-micro cable between my computer and the board's own micro usb port for power, I'm able to see my board in the Vivado Hardware manager.

In the Vivado hardware manager, with the board connected, it says "Device xc7z020 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it." I can click Program Device, but I don't know what to load into it.

If someone could just point me in the direction of the best documentation to read to get familiar again with this process, that would be awesome. I've never actually used this board for FPGA development (the Zynq 7020 dev board may be old now, but it's new to me), and only briefly touched on VHDL about 10+ years ago like I said. I want to switch from VHDL to Verilog, but need to study up on it. I also don't remember how to use Vivado.

Thank you,

Rich C.

Are the PCB and Schematic design files available for the MicroZed AES-Z7MB-7Z010-SOM-I-G/REV-H ?

byoung — Wed, 02 Apr 2025 12:56:20 GMT

Are the PCB and Schematic design files available for the MicroZed AES-Z7MB-7Z010-SOM-I-G/REV-H ?

What CAD program was used, Altium?

RE: Are the PCB and Schematic design files available for the MicroZed AES-Z7MB-7Z010-SOM-I-G/REV-H ?

byoung — Mon, 07 Apr 2025 12:00:59 GMT

yes use. LOL

RE: Where to start: MicroZed 7020, Vivado 2024.2, Ubuntu 24.04

eNtropy618 — Sat, 05 Apr 2025 21:49:29 GMT

oh cool. I didn't know you could fit Ubuntu on it.

I'll have to learn more about Vitis, I don't remember using or hearing about that at all before. I did know you could compile single-purpose programs to run directly on an embedded cpu (or microcontroller?) without the bloat of an entire operating system... but I've never ventured down that path.

Side Note: I totally forgot how to even use Vivado, so I'm working my way through some of their documentation. I was thinking I'd first design or find some sort of logic and push that to the FPGA, but without I/O, it would be pointless. Having the serial console over USB is hella convenient, and I'd like to get an OS working on there.

RE: Where to start: MicroZed 7020, Vivado 2024.2, Ubuntu 24.04

eNtropy618 — Sat, 05 Apr 2025 21:43:53 GMT

Yes! Thank you. I knew about the MicroZed Chronicles and was looking into them when I first got my MicroZed board. I know it will probably be a bit dated, but I've got to start somewhere.

RE: Where to start: MicroZed 7020, Vivado 2024.2, Ubuntu 24.04

iksevas — Sat, 05 Apr 2025 21:35:42 GMT

MicroZed Chronicles by Adam Taylor has many articles that target the platform and will get you moving. Now it’s your turn to Google!

RE: Where to start: MicroZed 7020, Vivado 2024.2, Ubuntu 24.04

padudle — Sat, 05 Apr 2025 20:28:58 GMT

It is a very useful and satisfying thing you are planning to do. MicroZed is an ideal platform to get started on. A reasonably fast Ubuntu workstation is the best platform for FPGA development in my opinion. You can program just about any Zynq or ZynqMP using the free webpack version of the Vivado tools.

I like to run full Ubuntu Linux on the Arm processor itself but Petalinux can be a frustrating mess to start with. A good way to start is usint the Vitis --classic software development kit to writh so called bare metal applications. That gets you really close to the hardware in the PL and the PS. The IP Intergrator tool works pretty well and anything done in it will exported in the .xsa file that Vitis uses to make the necessary C header files.

Good luck.

RE: Where to start: MicroZed 7020, Vivado 2024.2, Ubuntu 24.04

eNtropy618 — Sat, 05 Apr 2025 17:53:21 GMT

Note: This should be an easy question to answer. Please don't flame me for not googling. I'm just feeling overwhelmed. Thank you.