Hi,
I try to use a PCIe to PCI adapter on Zynq Minit-itx board.
Link to PCIe to PCI adapter: http://www.startech.com/Cards-Adapters/Slot-Extension/PCI-Express-to-PCI-Adapter-Card~PEX1PCI1
I use the PCIe root complex design provided at http://zedboard.org/content/zynq-mini-itx-7z045-pcie-design-vivado-20144
I use version 2014.4 for petalinux tools, Vivado and SDK.
After generating bitstream, FSBL, u-boot and kernel I test PCIe with Ethernet device.
PCIe root complex work, I connect an ethernet PCIe device to test it. Below, a log of PCI initialization when the PCIe ethernet is connected:
xaxi_pcie_init_port: LINK IS UP
AXI PCIe Root Port Probe Successful
xaxi_pcie_set_bridge_resource:pci_space: 0x02000000 pci_addr:0x0000000060000000 size: 0x0000000010000000
xaxi_pcie_set_bridge_resource:Setting resource in Memory Space
PCI host bridge /amba_pl/pciex@50000000 (primary) ranges:
MEM 0x0000000060000000..0x000000006fffffff -> 0x0000000060000000
PCI: PHB MEM resource 0 = 0000000060000000-000000006fffffff [200]
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
pci_bus 0000:00: root bus resource [io 0x1000-0xffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
PCI: bus0: Fast back to back transfers disabled
PCI: bus1: Fast back to back transfers disabled
pci 0000:00:00.0: BAR 0: no space for [mem size 0x40000000]
pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x40000000]
pci 0000:00:00.0: BAR 14: assigned [mem 0x60000000-0x600fffff]
pci 0000:00:00.0: BAR 13: assigned [io 0x1000-0x1fff]
pci 0000:01:00.0: BAR 4: assigned [mem 0x60000000-0x60003fff 64bit pref]
pci 0000:01:00.0: BAR 2: assigned [mem 0x60004000-0x60004fff 64bit]
pci 0000:01:00.0: BAR 0: assigned [io 0x1000-0x10ff]
pci 0000:00:00.0: PCI bridge to [bus 01]
pci 0000:00:00.0: bridge window [io 0x1000-0x1fff]
pci 0000:00:00.0: bridge window [mem 0x60000000-0x600fffff]
The kernel boot and I can view the device in a lspci.
When I connect the PCIe to PCI adapter the kernel lock during PCI initialization. Below, a log of PCI initialization when PCIe to PCI adapter is connected:
xaxi_pcie_init_port: LINK IS UP
AXI PCIe Root Port Probe Successful
xaxi_pcie_set_bridge_resource:pci_space: 0x02000000 pci_addr:0x0000000060000000 size: 0x0000000010000000
xaxi_pcie_set_bridge_resource:Setting resource in Memory Space
PCI host bridge /amba_pl/pciex@50000000 (primary) ranges:
MEM 0x0000000060000000..0x000000006fffffff -> 0x0000000060000000
PCI: PHB MEM resource 0 = 0000000060000000-000000006fffffff [200]
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
pci_bus 0000:00: root bus resource [io 0x1000-0xffff]
pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
pci_bus 0000:00: scanning bus
pci 0000:00:00.0: [10ee:0706] type 01 class 0x060400
pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x3fffffff]
pci 0000:00:00.0: calling pci_fixup_ide_bases+0x0/0x3c
pci_bus 0000:00: fixups for bus
PCI: bus0: Fast back to back transfers disabled
pci 0000:00:00.0: scanning [bus 01-07] behind bridge, pass 0
pci 0000:00:00.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:01: scanning bus
pci 0000:01:00.0: [12d8:e111] type 01 class 0x060400
pci 0000:01:00.0: calling pci_fixup_ide_bases+0x0/0x3c
pci_bus 0000:01: fixups for bus
PCI: bus1: Fast back to back transfers disabled
pci 0000:01:00.0: scanning [bus 00-00] behind bridge, pass 0
pci 0000:01:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
pci 0000:01:00.0: scanning [bus 00-00] behind bridge, pass 1
pci_bus 0000:02: scanning bus
After this line the kernel is locked, no other information is printed and no boot.
The PCIe to PCI adapter is OS independant (No additional drivers or software required).
I test it on a standard PC (with BIOS), it worked.
I don't understand what is wrong in this configuration.
Do I need to update my device-tree with information about the PCIe to PCI adapter ?
Or hardware compatibility issue between PCIe to PCI adapter and PCIe root complex Xilinx design ?
Best regards,
Hugo
