hello everyone,
for the moment i do the HW zedboard training and i reach about this moment to lab7 when we customize our IP and create our IP core .
I'm don't very familiar with vhdl and verilog and with the assumption that this lab will come very handy in the future I would like to go deeper in the vhdl and verilog files and see the all picture.
therefore I would like if you all suggest or share a verilg & vhdl cheatsheet which include the commands and syntax required and their explanations.
thank you in advance .
