MiniZed Hardware Design - Recent Threads

About Programming and Obtaining Configuration Files for IRPS5401MTRPBF

sdimen — Tue, 25 Mar 2025 09:54:30 GMT

Hi everyone,

I am designing a custom carrier board and plan to use Infineon's IRPS5401MTRPBF PMIC with the UltraZed-EG SOM. I understand that the device needs to be programmed to meet specific power requirements.

Programming Method: Programming of the IRPS5401MTRPBF requires the use of the PowIRCenter tool provided by Infineon. The tool allows the user to configure the PMIC's output voltage, startup sequence, and other parameters according to specific application requirements.

Configuration File Obtaining: If you want to use the same configuration as the UltraZed-EG SOM carrier board, you can contact the relevant designer or community member to obtain the PowIRCenter configuration file for the design. In previous discussions, the designer has indicated that such a configuration file is available.

Pre-programmed device procurement: Typically, the IRPS5401MTRPBF is supplied in an unprogrammed state. If you need a pre-programmed device, you may need to contact a vendor or use a programming service. For example, Avnet offers a device programming service that can be customized to your needs.

Arduino expansion shield ports

jimmi1 — Thu, 07 Nov 2024 15:08:52 GMT

Can the arduino expansion ports be driven directly from the programmable logic or is it necessary to pass through the PS?

RE: Arduino expansion shield ports

iksevas — Thu, 07 Nov 2024 16:42:42 GMT

On MiniZed the Arduino expansion ports are on BANK 34 - This is a PL (FPGA) bank and not the PS (MIO Bank).

Can MInized drive stepper Motor driver ULN2003A?

koseiyokoyama — Fri, 07 Jun 2024 01:14:14 GMT

Can Minized drive Stepper motor driver (one in ELGOO kit) ?

Motor driver uses TI ULN2003A IC to dirve stepper motor (28BY-J-48)

I wrote RTL to drive stepper motor driver from Minized GPIO,

but it does not seems GPIO drive stepper motor driver

thank for your help

RE: Can MInized drive stepper Motor driver ULN2003A?

javagoza — Thu, 27 Jun 2024 08:02:32 GMT

I'm glad you solved it. Watching a stepper motor work with your own development is very rewarding.

RE: Can MInized drive stepper Motor driver ULN2003A?

koseiyokoyama — Thu, 27 Jun 2024 00:46:14 GMT

Thanks, Javagoza,

I have done your suggestion and finally stepmotor is stepping!

again, thanks for your help!!

RE: GPIO can be used as input/output port?

koseiyokoyama — Mon, 24 Jun 2024 08:10:39 GMT

Thank you so many help!!

I finally make my RTL working!

the keys are

use Global option when Generate output Objects...

use PULLUP(inout signal port);

assign inout_port = output_enable ? output_reg : 1'bZ;

in RTL

use set_property PULLUP true [get_port inout_port] in xdc

thanks again!!

GPIO can be used as input/output port?

koseiyokoyama — Wed, 19 Jun 2024 02:37:13 GMT

I am trying to comunicate with Temp/Humid module DHT11
However data pin should be pull up to 3.3 but while my RTL trying to comunicate with DHT11 throgh IO13 pin, Data line pull down to GND.
if GPIO can be inout port, then any one know how?

My RTL working fine in simulation with Vivado

RE: GPIO can be used as input/output port?

jc2048 — Wed, 19 Jun 2024 21:31:39 GMT

Here's the thread that I dimly remembered, in case it's of any use to anyone:

/technologies/fpga-group/f/forum/50650/vivado-and-zynq-tri-state-help/197015

RE: GPIO can be used as input/output port?

michaelkellett — Wed, 19 Jun 2024 16:52:48 GMT

The advantage of the external MOSFET approach is that the output of your FPGA is protected if you get things wrong. Most FPGAs don't offer a real open drain output so you end up having to never slip up with your code to avoid the FPGA sometimes pulling up an external active pull down.

In the OP's case I'd recommend this since adding a MOSFET to his sensor is not a big deal.

RE: GPIO can be used as input/output port?

jc2048 — Wed, 19 Jun 2024 16:46:42 GMT

I think this has cropped up here before and is actually an issue with how the Vivado top-level wrapper works and how you get the tristate control (that I presume you're using to implement the open-drain) to propagate up from your code level, one step down from the wrapper. I seem to remember (vaguely) something about a specific naming convention you have to use for the two drive signals (output signal and tristate control) in order for Vivado to understand what you're asking for and create a wrapper with the tristate implemented up at the actual pin.

RE: GPIO can be used as input/output port?

shabaz — Wed, 19 Jun 2024 13:41:59 GMT

It seems a waste to use such a sensor directly attached to a MiniZed. There are better sensors, that interface through more normal interfaces.

One typical approach to connect such a sensor, is to use two ports; one as input, and the other as output, and build yourself an interface. You'd have to check if the values below are appropriate (I've not read the DHT11 datasheet). With such an interface circuit, the controller (FPGA or microcontroller or otherwise, it's up to you) doesn't need to switch between input and output.

When a logic high is sent by the controller, the sensor line is pulled low. When a logic low is sent by the controller, the line is pulled up, and the remote sensor is free to pull the line low.

RE: GPIO can be used as input/output port?

embeddedguy — Wed, 19 Jun 2024 11:25:01 GMT

As you are using DHT11 sensor, you should use Serial protocol i.e. UART RX line to sample the received values.

The DHT11 sensor works like following.

"Data line remains in high normally, then master in this case FPGA will start communication first. The the sensor will respond with temparature, humidity data".

See the following image of timing diagram.

The output given out by the data pin will be in the order of 8bit humidity integer data + 8bit the Humidity decimal data +8 bit temperature integer data + 8bit fractional temperature data +8 bit parity bit. To request the DHT11 module to send these data the I/O pin has to be momentarily made low and then held high as shown in the timing diagram below

components101.com/.../dht11-temperature-sensor

RE: Can MInized drive stepper Motor driver ULN2003A?

koseiyokoyama — Tue, 18 Jun 2024 07:26:55 GMT

Thanks for your replys. I will be back to this project in couple of weeks

Minized System generator hardware in the loop

jimmi1 — Sat, 01 Jun 2024 18:22:41 GMT

I would like to ask if anyone has experience or has managed to achieve hardware in the loop simulations using the minized board in matlabs system generator. I'm not sure if it is possible to enable the JTAG interface and whether or not board definition files exist for system generator.

Thanks.

RE: Minized System generator hardware in the loop

jimmi1 — Tue, 11 Jun 2024 20:59:30 GMT

For system generator you do need a licence yes. The system generator gives several evaluation boards such as Artix 7 but for unsupported boards it does require definition files. I have never done it before was wondering if anyone had.

RE: Can MInized drive stepper Motor driver ULN2003A?

javagoza — Fri, 07 Jun 2024 06:38:10 GMT

The first thing you need to check is if the signal on the GPIOs you are using is correct. At the logic level, you can use the ILA (Integrated Logic Analyzer) on the FPGA and observe from Vivado. If the logic is correct, then check without connecting the ULN2003A if the voltage levels that the Minized gives you are sufficient for TTL, greater than 2V1.

RE: Minized System generator hardware in the loop

flyingbean — Wed, 05 Jun 2024 15:28:57 GMT

Do you need a Matlab license to do hardware-in-loop on FPGA platform? System generator should not need a board definition files. The flow to generate bitstream will need the board definition files.

minized : how to define master clock in xdc for RTL

koseiyokoyama — Thu, 02 May 2024 06:10:35 GMT

I designed 7seg display driver in Verilog.
in xdc file, I define my clock as follows

set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS33} [get_ports clk];

create_clock -add -name sysclk -period 20.000 -waveform {0.000 10.000} [get_ports clk];

L12 is WRCC Pin

and clk is my clock input pin in my RTL design

it does not seem clock is clocking..

Am I missing something?

Block design is not used.

RE: minized : how to define master clock in xdc for RTL

javagoza — Wed, 08 May 2024 09:12:58 GMT

I'm glad it worked for you. The Minized is a great development board to get started with FPGAs. I have a musical synthesizer project made with the Minized, still half done waiting to find time to finish it.

AMD Zynq SoC MIDI Vintage Sound Synthesizer - Final

RE: minized : how to define master clock in xdc for RTL

koseiyokoyama — Wed, 08 May 2024 00:24:09 GMT

Yes, Boot from flash worked!! Thank you!!

Vitis did not work.... any way, I can back to my project!!

RE: minized : how to define master clock in xdc for RTL

javagoza — Tue, 07 May 2024 10:13:52 GMT

May be the ZYNQ7 PS is not programmed. First, you can try to boot the Minized from flash memory and then reprogram FPGA from Vivado.

Or export hardware project and program flash with Vitis using the "Hello world" application.

RE: minized : how to define master clock in xdc for RTL

koseiyokoyama — Tue, 07 May 2024 09:12:44 GMT

Hi Javagoza,

I tried NO2 , i.e. without SDK, it is programmed but it does not seems clock is automaticaly started.
LED is not blinking...

do you have any idea how I give queue to FPGA? or any option I have to set?

And thank to helpful links!!

RE: minized : how to define master clock in xdc for RTL

javagoza — Tue, 07 May 2024 08:14:23 GMT

[quote userid="501034" url="~/products/devtools/avnetboardscommunity/avnetboard-forums/f/minized-hardware-design/54576/minized-how-to-define-master-clock-in-xdc-for-rtl/221254"]1. I guess if you use block design you need HDL wrapper, correct?[/quote]

You're right and this is the easy way. After that, you can parse the output files and discover how the automatic instantiates the PS If the wrapper bothers you.

[quote userid="501034" url="~/products/devtools/avnetboardscommunity/avnetboard-forums/f/minized-hardware-design/54576/minized-how-to-define-master-clock-in-xdc-for-rtl/221254"]2. with this way, program FPGA will work? I mean without SDK...[/quote]

Why don't you try it?

[quote userid="501034" url="~/products/devtools/avnetboardscommunity/avnetboard-forums/f/minized-hardware-design/54576/minized-how-to-define-master-clock-in-xdc-for-rtl/221254"] I want to output signal to GPIO(Arduino IO0 ~ IO10 for instance), following xdc definition would be correct?[/quote]

Seems ok.

https://github.com/Avnet/hdl/blob/master/Boards/MINIZED/minized_pins.xdc

I have some examples of a 7-segment LED driver for the Spartan 7 FPGA.

SystemVerilog Study Notes. Hex-Digit to Seven-Segment LED Decoder RTL Combinational Circuit

RE: minized : how to define master clock in xdc for RTL

koseiyokoyama — Tue, 07 May 2024 00:23:41 GMT

Hi javagoza,

Thank you for quick and detailed replay!!

Now I have three more questions.

1. I guess if you use block design you need HDL wrapper, correct?

2. with this way, program FPGA will work? I mean without SDK...

3. I want to output signal to GPIO(Arduino IO0 ~ IO10 for instance), following xdc definition would be correct?

if so, do I have to add pin to my module or they will be out put from system7 GPIO?

too many questoins.... but Please help me
Thanks,

part of my xdc

set_property PACKAGE_PIN R8 [get_ports {GPIO_Out[0]}];

set_property PACKAGE_PIN P8 [get_ports {GPIO_Out[1]}];

set_property PACKAGE_PIN P9 [get_ports {GPIO_Out[2]}];

set_property PACKAGE_PIN R7 [get_ports {GPIO_Out[3]}];

set_property PACKAGE_PIN N7 [get_ports {GPIO_Out[4]}];

set_property PACKAGE_PIN R10 [get_ports {GPIO_Out[5]}];

set_property PACKAGE_PIN P10 [get_ports {GPIO_Out[6]}];

set_property PACKAGE_PIN N8 [get_ports {GPIO_Out[7]}];

set_property IOSTANDARD LVCMOS33 [get_ports {GPIO_Out[*]}];