IP Catalog with IP Integrator

Hi

I have a Picozed Z030 and the FMC Carrier. I want to implement Aurora 8b/10b on it. I open the example, and I got all the vhdl files, but I donu00B4t know how to connect the init_clk, drp_clk and the GT_REFCLK signals in the design. How can I route the clocks from the zynq for connecting with the external signal required in the IP Catalog Aurora example.
I need 1 single clock for DRP_CLK and a differential clock for INIT_clk, both 50MHz and, 125MHZ for GT_REFCLK

0 zedhed over 8 years ago

Hi abhaya,

Have you taken a look at PG046 and XAPP1193 yet?

http://www.xilinx.com/support/documentation/ip_documentation/aurora_8b10b/v10_1/pg046-aurora-8b10b.pdf

http://www.xilinx.com/support/documentation/application_notes/xapp1193-aurora-8b10b-on-kc705.pdf

Although XAPP1193 is related to Kintex devices, most of the work for Aurora8b/10b is around the transceivers so most of the information should still be applicable.

Regards,

-Kevin
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 Former Member over 8 years ago

Thank you for the answer. I already look at that files, but my problem is how to define init_clk, drp_clk in my <file>.xdc using the picozed. How do I get these signal from the PS ?
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 zedhed over 8 years ago

Hi abhaya,

Perhaps I am misunderstanding your question.

If you are connecting those signals externally to the Zynq device, then look within your top level HDL for the port names and then you can use those port names for your XDC pin constraints.

If you are connecting those signals directly to the Zynq Processing System, then you simply make the connection within the IP Integrator Block Design and then there is no need for an XDC pin constraint.

Regards,

-Kevin
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel