PicoZed 7030 SFP+ Design based on Xilinx Aurora Core

Prashant,

My comments/thoughts on your items above:

1)

Per this schematic, on page 3:

http://zedboard.org/sites/default/files/documentations/PZCC_FMC_RevC_Schematic_0.PDF

Placing a Jumper on JP6 will set SEL_B to 1, selecting Input 1, which is the MGTCLK_SYNTH output of the CDCM61002RHB part.

This produces a clock that goes to the MGTREFCLK1 signals pair, which goes to the JX3 connector on page 9.

On the PicoZed, this goes to the MGTREFCLK1 signal on bank 112, seen on page 4 here:

http://zedboard.org/sites/default/files/documentations/PicoZed_7015_7030_Rev_C.PDF

2)

Make sure you are looking at the board correctly, and it is not upside down.

3)

How do you know this?  Are you bringing in the clock to a IBUFDS_GTE2 buffer and using the O output, and not the ODIV2 output?

----

I would put some ILA cores into the design and poke around to see what is going on.  How did you configure the Aurora core?  Are you using a reference design? 

Hi there,

While Tim makes some good points, I'll chime in here.

First, I do not think your issues are on the PicoZed 7030 SOM.  I think it is a configuration issue on the PicoZed Carrier Card.

Next, please let me direct you to the Errata documentation.
Go to this page:
http://picozed.org/support/documentation/4701

then, under Hardware Guides "PicoZed FMC Carrier Card Rev C Errata"

There are many components and changes that you will need to perform on pages 8-10, some directly influence the SFP+ for this board.  Once you have completed those modifications, we can start to look at your other issues.

1) You are correct that you need to leave JP6 disconnected in order to get the MGT clock sourcing from the Synthesizer.  This is how I run the board.  I agree the wording CAN be misleading.  I believe the confusion comes from revisioning the board and not updating the silkscreen to be more clear.

2) For this question, please see the above errata linksand perform all necessary rework.  Next, let's validate that your crystal is not damaged.  I would suggest you set your SW9+SW10 to 000110, where 0 is defined as the switch being placed towards the card edge, which also aligns with the text on the SW component.  This will give you 250MHz.  I tested this and it does for me.  At this point please wire the SMAs or SFP+ with a loopback adapter/cables.  I would then suggest you run an IBERT test with 3.25Gbps at 250MHz.  If that works then we can be certain your clocking circuit is fine.  I have linked a reference design in question 3 if you need assistance running / setting up IBERT.

3) We can easily check this by using the known good configuration I defined above and use an IBERT.  You can follow the IBERT tutorial here:
http://picozed.org/support/design/4701/76
Search for IBERT.  It should be one of the last designs on that page.
Once you have successfully tested this, you will know that your clock is setup properly to at least run the IBERT and it will be a matter of working out why you are not getting 156.25MHz as you are intending.

You can also see the page:
http://picozed.org/support/trainings-and-videos

Search for
Tech Tip - Transceiver Tools 101 through 104.  They can help you setup IBERT and tune your circuit.

--Dan

Hi there,

I almost did not remember to mention this: There is a laser ENABLE that is default set to DISABLING the laser. To ensure your SFP+ module is enabled to even run, you need to pull that line LOW. An example of this can be seen in the above posted IBERT design. Please check that as well!

--Dan

Hi Dan,

1. JP6 ON has to mean jumper ON. Please change the documentation if you can to mention it. If you also print it on the PCB it is an error.

2. The point is that I get 62.5 MHz for all 0s and around 235 MHz for 000110. This I checked before writing on the forum. I get 125 MHz for 000010 at SW9+SW10. The board is NOT upside down.

3. I am using 6.25 Gbps optical link. I already did the IBERT procedure with 250 MHz and could get a result with JP6 off (I get 6.113 Gbps which I amount to the fact that the SFP+ clock frequency is less than 250 MHz). The problem comes when I try a clock other than these two which happens to be my design necessity. I should mention that I get the outputs from SMA J15 & J16.

4. I checked it for all the three boards that I have.

5. I am using TX_DISABLE = '0', SFP_MODDEF_1 = '1',tSFP_MODDEF_2 = '1', SFP0_RATE_SEL = '1' in my design. My SFP+ module is Finisar FTLX8574D3BCV. I also find that the FMC board circuit lacks the necessary 4.7k pullup resistors. Making SFP_MODDEF_1 and SFP_MODDEF_2 = '0' would essentially start the I2C cycle for the SFP+ modules.

6. I am using Vivado 2015.4.2 for the operation with Aurora 64b66b version 11.0. If you could let me know the combination which generates 156.25 MHz correctly I can go forward.

7. I did not find any way to use an external DIFF_CLK signal to drive the FPGA. Can you please suggest one?

Thanks in advance.

Regards,
Prashant

Hi there,

Were you able to take care of the items in the errata?  You will need to complete those in order to ensure the transceiver link is given every advantage.

To answer your points:
1. Yes, it means Jumper installed or not

2. Based on your measurements, I believe that you are getting the clocks you want and possibly have a measurement issue.  Remember that these are differential outputs - you will require test equipment capable of measuring that.  I have tested the above configuration on my end and get 250MHz.  Swapping SOMS will not help, this is a circuit that is located on the carrier card.  If you have another carrier card to test with I would try that, however I would ensure that all the necessary rework has been performed, per my earlier comments.  Note, if you have not performed the rework, there are additional components included on the board that potentially could be skewing your measurements.

3. I would not attribute the clock speed to the data rate.  If the clock speed did not match what you requested, and you were following the IBERT procedure I linked to above, the design would not run. The external clock only drives the MGT PLL, which is a VERY high precision clock generation circuit.   Not only would the logic side clock that is generated from the incoming MGT clock not be locking, but the MGT itself would not lock.  These clocks depend on the configuration, which would have been set to look for 250MHz.  The data rate is effected by the protocol configuration, PRBS setting as well as other miscellaneous configuration.  The 6.25Gbps is the raw speed, not your data rate.

4. As I mentioned in my previous reply as well as #2 above, I do not think it is a SOM issue nor do I think swapping the SOM can correct your issue.

5. You mention FMC board circuit, I am confused, are you using a FMC to SFP adapter board?  If so, which board?

6. I think the user guide is accurate and a 010100 will give you 156.25MHz.  You can validate this by running the above linked IBERT design, however configure it by HAND and substitute 156.25MHz for 250MHz.  You might have to change the QPLL setting depending on the clock vs. data protocol configurations (I know you need to do this to use a 5.0Gbps).  See page 8 of the User Guide:
http://picozed.org/support/documentation/4701
search:
PicoZed FMC Carrier Card Hardware User Guide

7. You can either use a board like the HighTechGlobal PCI Express Test & SerialIO Expansion Module or a FMC card. 
*If you choose the PCIE path, note that on a PicoZed FMC v1, this clock passes through a jitter attenuator which will limit you to PCIe clock frequencies (100MHz, 125MHz, or 250MHz). 

*If you choose the FMC path, ensure JP6 is installed. 
*If you can get a XM107 board, it comes with a Silicon Labs clock on it that is programmable.  The one I have used defaults to 156.25MHz. 
*It might be easier to get a XM104, which also has a clock on it.  I am not aware what it defaults to or what the clock is connected to.

Please let me know if you performed the rework in the errata.

--Dan

Hi there,

After you validate the above actions, you can attempt to use this for your 156.25Mhz configuration.  I believe that among the other issues you have described, the circuit vs. label vs. description might be confusing.
In #6 above, I mention 010100 as the configuration to get 156.25MHz.  While this is true, I believe that the confusion is translating that to the SWITCH configuration.

Please note the header in the table vs. signal names in the schematic.  To apply this configuration to the BOARD (SW9SW10) the first position of each switch is on the RIGHT hand side.  From a BOARD switch position perspective, I believe you will want:

SW9   SW10
10    0010

CARD EDGE