I am using Picozed 7030 with a FMC carrier board rev. C to test SFP+ loopback. There are different problems that I encounter.
1. The MGT_CLK select jumper JP6 in description says ON = MGT_CLK and OFF = FMC_CLK. But a closer review of the schematics shows that keeping the jumper ON makes the clock multiplexer SY89853u to select FMC_CLK instead of MGT_CLK.
2. The clock synthesizer CDCM61002RHBT synthesizes false frequencies for the given/recommended settings of the switches SW9 and SW10. For example,
156,25 MHz is not generated by the synthesizer if SW9+SW10 is 010100. Instead it generates 65 MHz. 125 MHz is generated when SW9+SW10 reads 000010 and not as specified in the Hardware user guide.
3. The MGT clock is not forwarded to MGT clock pins.
Can someone help with these issues?
I have three PicoZed 7030 boards and each has these problems.
Thanks & Regards,