While designing a carrier board for the picoZed Z7030 module I noticed the following regarding the voltage levels of these signals. Both signals are sourced by the open drain PG (powergood) pin of a TI TLV62130 switching regulator as well as a voltage divider between a specific power rail and ground (described below).
The pullup resistor is required as the PG signal is open drain. The assumed purpose of the pulldown resistor is to establish a low signal level before the regulator has enough supply voltage to drive the OD signal low/deasserted. An issue is that the divider reduces the high level output voltage, reducing the high level voltage margin.
VCCIO_EN (PG_1V8 on PZ schematic) is the PG output of the 1.8V regulator. The voltage divider is a 1.5K pullup to 1.8V and a nominal 5K pulldown to ground. When the regulator PG pin is released the high logic level is nominally 1.38V. If the carrier were to treat this as a 1.8V logic level when monitoring VCCIO_EN, then there is very little margin between the 1.38V logic level and VIH(min) for a LVCMOS18 logic level. For LVC logic devices, VIH(min) = 1.17V, yielding a 210mV nominal margin.
If the pulldown resistor were increased to 10K, VOH increases to 1.57V and voltage margin is a more comfortable 400mV.
PG_MODULE is the PG output of the 1.8V regulator. The voltage divider is a 1K pullup to 3.3V and a nominal 5K pulldown to ground. This signal is driven by the carrier board, but may also be monitored by the carrier board to indicate that picoZed+carrier power is good. As with the VCCIO_EN signal, the resistive divider decreases VOH, but not as significantly as with VCCIO_EN.
The concern is with the 1K pullup to 3.3V, which causes the TLV62130 PG pin to nominally sink 3.3 mA. The TLV62130 data sheet only guarantees VOL(min) = 0.3V for PG sink current of 2mA max. Since PG_MODULE drives PS_POR_B, by design VOL(min) doesn't have a guaranteed level from the TLV62130. VOL(max) for PS_POR_B is 0.8V.
To operate the TLV62130 pin under the 2mA max spec'd sink current, the pullup resistor could be doubled to 2K and the pulldown to 10K.
The VCCIO_EN resistive divider doesn't adversely affect the logic high level, as the regulator PG pin is released the high logic level is nominally 2.53V. If the carrier treats this as a 3.3V logic level when monitoring PG_MODULE, VIH(min) for a LVCMOS33 logic level is 2.0V, yielding a 530mV logic high margin.
Neither of the above are critical issue, but worth noting. Please respond if the above analysis is incorrect.
NOTE TO AVNET: There is an minor error in figure 5 of PicoZed Hardware User Guide. The 1.8V, 3.3V, and DDR3L regulators are mistakenly labeled as TLV61230 (instead of TLV62130). This tripped me up when a search for that part number had no results. A quick peek at the schematic resolved the mystery.