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PicoZed Hardware Design onsemi_vita_cam IP vita_clk partially routed
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  • picozed vison vita fmc
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  • python1300
Related

onsemi_vita_cam IP vita_clk partially routed

durmusk
durmusk over 3 years ago

Hi all,

 

I'm working on a custom board based on PicoZed 7020 SOM design. It has the same Zynq part number (XC7Z020-1CLG400). The board has a Python1300 camera sensor interface (again, a custom one, not FMC interface). However, the crucial difference is that some LVDS pins are connected to different banks on the FPGA.

 

I'm trying to adapt fmchc_python1300c project to this board. The first problem was that since LVDS pins are not all on the same bank, there were routing problems about BUFR clocks being on different regions. When I looked at onsemi_vita_cam IP, I've seen that there are options whether or not to use regional clocks. By default, it was enabled. I have changed it not to use regional clock.

 

in onsemi_vita_cam_core.vhd, line 981

USE_HS_REGIONAL_CLK => FALSE

 

That solved the BUFR problem, but naturally it led to some other issues. One particular routing problem that I cannot solve is that vita_clk inside the onsemi_vita_cam IP does not get fully routed.

[DRC RTSTAT-2] Partially routed nets: 1 net(s) are partially routed. The problem bus(es) and/or net(s) are bd_i/onsemi_vita_cam_0/U0/onsemi_vita_cam_v3_1_S00_AXI_inst/vita_clk.

There is not any more info on Vivado about the error. I am looking for pointers on how to resolve this issue.

 

The same problem can be reproduced on PZ7020 fmchc_python1300c project by changing USE_HS_REGIONAL_CLK to FALSE as mentioned above.

 

Thanks,

Durmus

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Top Replies

  • drozwood90
    drozwood90 over 3 years ago +1 suggested
    Hi there, The clock is likely not being routed because it physically cannot be routed. You can take globals and reach all regions, but you cannot go the other way around. You want to avoid or at the very…
  • drozwood90
    0 drozwood90 over 3 years ago

    Hi there,

     

    The clock is likely not being routed because it physically cannot be routed.  You can take globals and reach all regions, but you cannot go the other way around.  You want to avoid or at the very least minimize pinning out the way you described as it is really hard to move regional clocks around.  You also NEED to use LVDS pairs as PAIRS if you need LVDS.  You will probably need to add a constraint to move the clocks to globals.  That will allow you to branch that out to the regions, however, then you will have issues with timing the data.  If you can get this to work, expect long build times.

     

    Having high speed things like this spread across regions like that, really makes the tools struggle to meet timing and will probably cause you problems throughout development.

     

    --Dan

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