• How to generate PCIe clock when configured as PCIe root complex...

    QUESTION 1:

     

    Let's say I configure PCIe in Zynq 7000 FPGA as a root complex, where does the PCIe clock come from in this case?

     

    I look at the schematics and it appears that the PCIe_REFCLK is an output of the edge connector?

     

    Does that mean the PCIe_REFCLK…