I have a basic design with DRAM and UART1 configured in PS and PL LEDs with pattern Ah.  -> OK

Zynq FSBL + Zynq DRAM tests application project in SDK --> OK

Created BOOT.mcs (fsbl.elf, system.bit, dram_test.elf) -> OK

Programmed the BOOT.mcs into…

I'm using a PicoZed 7015 with Xilinx SDK 2018.3 in a bare-metal application. Everything works reading and writing to the eMMC with the default setting of ECC disabled. I have a high reliability application in mind and I'm wondering what would happen if…

We have been successful downloading FLASH with Vitis 2020.1.  During a download session, the user cancelled the download in midstream and the board became a brick.

We tried to re-download the Flash and we get  message: uboot error and Flash programming initialization…

Hello,

In Vitis, I am creating a Linux Application Project and the application project settings when creating a new domain automatically selects OpenCL under supported runtimes. OS is set to Linux in the drop down and processor PS7_CortexA9 however I…

Hello,

I am using a PicoZed with petalinux 2020.2 and Vitis 2020.2. I have been trying to debug over Vitis using tcf via ethernet connection. I have set up my local pc to a local IP and set up the picozed upon boot to a different IP on the same subnet…

Dear All,

I am making a carrier board for the Picozed, and I was wondering if it is possible to swap pairs for the ethernet lines (not polarity swapping, but pairs e.g. 3<=>4)

Thank you all,

Peter

With Picozed seemingly marked as out of stock until at least November 2021, I'm worried it is realistically semi end of life.

Can anyone from Avnet comment of the plan for PicoZed hardware supply moving forward? (For reference I've been using 7030…

Dear Sir,

We are using Picozed boards and it has Zynq-7020 SoC. We completed our design and functional tests but during environmental tests, we have faced very strange problem.

In the attached FSBL debug output file, “reboot status register” values can…

I working with a custom board built with a PicoZed 7030 module.  The USB host circuitry was modeled after the PicoZed carrier card.  USB memory gadgets work, but no attached slave devices work (no hubs, no mice, etc.)

When the USB driver tries to enumerate…

Can improper sequencing of the PicoZed SOM Vin, PWR_ENABLE and VCCIO_EN cause actual damage to the PicoZed Card?

In my application, I do not think I am handling the power-off sequencing correctly and Vin and power enable drop nearly coincidentally.

The…

Does anyone know where I can find the Altium schematic and layout files for the 7030 PicoZed SOM and FMC Carrier Card V2 boards?

Hi all,

I'm working on a custom board based on PicoZed 7020 SOM design. It has the same Zynq part number (XC7Z020-1CLG400). The board has a Python1300 camera sensor interface (again, a custom one, not FMC interface). However, the crucial difference…

i am using Picozed 7030. The bank 500 MIO pins (MIO 0 and 9-15) are multiplexed with the on-board EMMC device

There is a multiplexer between the two uses - MIO or EMMC - which is connected by default to MIO 0 so it can be activated by SW.

My intention is…

Hello There,

    We are trying to get the PicoZed-SOM-7030 & FMC-CC-V2 setup working using the QSPI boot.

Setup

- AES-Z7PZ-7Z030-SOM-I-G/REV-E

- AES-PZCC-FMC-V2-G 

Xilinx SDK: 2019.1

We are using the new FMC-CC-V2 and a Xilinx JTAG platform cable.

We were…

Hello,

I'm currently working on a custom carrier board for the PicoZed 7030 board. I'm doing the design in Altium and as the design utilizes LVDS signals and some other high speed differential signals. So I would like to use the SI analysis tools built…

Hello,

I have a design that boots from QSPI on picozed board. The flash boot image consists of first stage boot loader (FSBL.elf),  FPGA (.bit) file and a standalone SDK application  (.elf) file (with TCP/IP Ethernet communication, no linux). I can program…

For the UltraZed Designer's Guide, there is a section that lists part numbers for the Cool Innovations heatsink and Sunon fan. I couldn't find such information for the PicoZed. Is this information available? And is there a heatsink and fan kit that I…

I am using the PicoZed 7010 (rev. C and E) with a custom carrier card, currently using VIN=+12V supply but would like to move to +15V. PicoZed HW Guide recommends +5/12V and limits max VIN=13.2V, but board components (TLV62130 and caps) appear to support…

Hello,

I am having trouble getting to boot the PicoZed board using JTAG. I have configured the DIP switches appropriately and using "petalinux-boot --jtag --kernel" seems to work as it is able to download the elf files and images at the corresponding…

Regarding,  "PicoZed SOM 7030 WITH FMC Carrier Card Version 2" board....

Daniel Rozwood was saying the IDT clock is programmable in a post entitled

"Re: power on reset frequency of pl_clk for PicoZed 7030 SOM + FMC Carrier V2"...

and…

"Xilinx Platform cable I" verses "Xilinx Platform Cable II"

Can you use the "Xilinx Platform Cable USB Model DLC9G" to program "PicoZed 7030 SOM + FMC Carrier V2" board?

I noticed the documentation says HW-USB-II…

Anybody know the power on reset frequency for the pl_clk clock on  PicoZed 7030 SOM + FMC Carrier V2 board?

I searched the picozed documentation and it doesn't say....  so without oscilloscope, i have no idea what it is...

QUESTION 1:

Let's say I configure PCIe in Zynq 7000 FPGA as a root complex, where does the PCIe clock come from in this case?

I look at the schematics and it appears that the PCIe_REFCLK is an output of the edge connector?

Does that mean the PCIe_REFCLK…

!  We hit a snag on the VCCIO_EN signal but I think we have it all sorted out but wanted to run it by you guys.

VCCIO_EN doesn't provide a 1.8V signal, it's more like 1.4V.  This was surprising to us as the HW user guide implies a 1.8V signal (although…

Hello,

I am trying to implement quad- ethernet using Picozed FMC carrier v2 + SOM 7030 + ospero OP031-1V8 quad fmc.

firstly i built the petalinux files as per this link

https://www.fpgadeveloper.com/2016/05/multi-port-ethernet-in-petalinux.html

https://github…