I'm working through the constraints for my custom carrier, and noticed it looks like the constraints file from the ADI reference project has the wrong MGT pins specified. According to the manual and schematics, the MGT pins on bank 111 are connected to the header pins (i.e. JX1 pin 87 is MGTREFCLK0_111_JX1_P on Zynq pin W6). The constraints file shows that as the bank 112 pin MGTREFCLK0_112_JX1_P on Zynq pin R6 (which the schematics show as not connected).
Can someone confirm that the constraints file is incorrect, and should instead be the corresponding bank 111 pins?
Oh, and I also noticed ccbrk_constr.xdc looks to have W17 and W14 swapped from their comments (not really critical, but may throw someone off copy/pasting the constraints to their own file... like me ;-) ).