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ZCU208 MTS error in RF_init.cfg

Alessio_

Hi,
I’m encountering an issue while implementing the MTS feature on the ZCU208 using MATLAB. From what I can see in the RF_init.cfg file, there seems to be a configuration problem. The initial setup appears to be correct and the MTS function starts properly, but afterwards other functions are called with incorrect arguments. Specifically, ResetNCOPhase is being applied to DACs 0 and 1, whereas on the ZCU208 the active DACs are 0 and 2. As a result, the log reports an error stating digital datapath 1 is not active. Should I manually modify the init file, or is possible to fix the problem in the MATLAB script instead?

Fullscreen RF_Init.txt Download 
SetExtParentclk 0 2
SetExtpllClkRate 0 8 2
SetExtpllClkRate 0 4 2
SetExtpllClkRate 0 1 2
SetupFIFO 0 0 1
SetupFIFO 0 1 1
SetupFIFO 0 2 1
SetupFIFO 0 3 1
SetupFIFO 1 0 1
SetupFIFO 1 1 1
SetupFIFO 1 2 1
SetupFIFO 1 3 1
SetDataPathMode 0 0 1
SetDataPathMode 0 2 1
SetDataPathMode 1 0 1
SetDataPathMode 1 2 1
SetDataPathMode 2 0 1
SetDataPathMode 2 2 1
SetDataPathMode 3 0 1
SetDataPathMode 3 2 1
SetClkDistribution 3 1 245.760000 3932.160000 1 1 5 1 245.760000 3932.160000 1 0 3 1 245.760000 3932.160000 1 0 5 1 245.760000 3932.160000 1 0 3 1 245.760000 3932.160000 1 0 5 1 245.760000 3932.160000 1 1 3 1 245.760000 3932.160000 1 0 5 1 245.760000 3932.160000 1 0
MTS_Sysref_Config 0 15 15
PAUSE
SetMixerSettings 1 0 0 1250.000000 0.000000 3 2 0 2 1
ResetNCOPhase 1 0 0
SetMixerSettings 1 0 2 1250.000000 0.000000 3 2 0 2 1
ResetNCOPhase 1 0 2
SetMixerSettings 1 1 0 1250.000000 0.000000 3 2 0 2 1
ResetNCOPhase 1 1 0
SetMixerSettings 1 1 2 1250.000000 0.000000 3 2 0 2 1
ResetNCOPhase 1 1 2
SetMixerSettings 1 2 0 1250.000000 0.000000 3 2 0 2 1
ResetNCOPhase 1 2 0
SetMixerSettings 1 2 2 1250.000000 0.000000 3 2 0 2 1
ResetNCOPhase 1 2 2
SetMixerSettings 1 3 0 1250.000000 0.000000 3 2 0 2 1
ResetNCOPhase 1 3 0
SetMixerSettings 1 3 2 1250.000000 0.000000 3 2 0 2 1
ResetNCOPhase 1 3 2
SetMixerSettings 0 0 0 -1250.000000 0.000000 3 2 0 3 1
ResetNCOPhase 0 0 0
SetMixerSettings 0 0 1 -1250.000000 0.000000 3 2 0 3 1
ResetNCOPhase 0 0 1
SetMixerSettings 0 1 0 -1250.000000 0.000000 3 2 0 3 1
ResetNCOPhase 0 1 0
SetMixerSettings 0 1 1 -1250.000000 0.000000 3 2 0 3 1
ResetNCOPhase 0 1 1
SetMixerSettings 0 2 0 -1250.000000 0.000000 3 2 0 3 1
ResetNCOPhase 0 2 0
SetMixerSettings 0 2 1 -1250.000000 0.000000 3 2 0 3 1
ResetNCOPhase 0 2 1
SetMixerSettings 0 3 0 -1250.000000 0.000000 3 2 0 3 1
ResetNCOPhase 0 3 0
SetMixerSettings 0 3 1 -1250.000000 0.000000 3 2 0 3 1
ResetNCOPhase 0 3 1
SetDecimationFactor 0 0 2
SetDecimationFactor 0 1 2
SetDecimationFactor 1 0 2
SetDecimationFactor 1 1 2
SetDecimationFactor 2 0 2
SetDecimationFactor 2 1 2
SetDecimationFactor 3 0 2
SetDecimationFactor 3 1 2
SetInterpolationFactor 0 0 2
SetInterpolationFactor 0 2 2
SetInterpolationFactor 1 0 2
SetInterpolationFactor 1 2 2
SetInterpolationFactor 2 0 2
SetInterpolationFactor 2 2 2
SetInterpolationFactor 3 0 2
SetInterpolationFactor 3 2 2
SetInvSincFIR 0 0 0
SetInvSincFIR 0 2 0
SetInvSincFIR 1 0 0
SetInvSincFIR 1 2 0
SetInvSincFIR 2 0 0
SetInvSincFIR 2 2 0
SetInvSincFIR 3 0 0
SetInvSincFIR 3 2 0
PAUSE
MTS_Sysref_Config 1 15 15
MultiConverter_Sync 1 -1 15
MultiConverter_Sync 0 -1 15
MTS_Sysref_Config 0 15 15
ResetNCOPhase 0 0 0
ResetNCOPhase 0 0 1
ResetNCOPhase 0 1 0
ResetNCOPhase 0 1 1
ResetNCOPhase 0 2 0
ResetNCOPhase 0 2 1
ResetNCOPhase 0 3 0
ResetNCOPhase 0 3 1
ResetNCOPhase 1 0 0
ResetNCOPhase 1 0 1
ResetNCOPhase 1 1 0
ResetNCOPhase 1 1 1
ResetNCOPhase 1 2 0
ResetNCOPhase 1 2 1
ResetNCOPhase 1 3 0
ResetNCOPhase 1 3 1
MTS_Sysref_Config 1 15 15
SetNyquistZone 1 0 0 1
SetNyquistZone 1 0 2 1
SetNyquistZone 1 1 0 1
SetNyquistZone 1 1 2 1
SetNyquistZone 1 2 0 1
SetNyquistZone 1 2 2 1
SetNyquistZone 1 3 0 1
SetNyquistZone 1 3 2 1
SetNyquistZone 0 0 0 1
SetNyquistZone 0 0 1 1
SetNyquistZone 0 1 0 1
SetNyquistZone 0 1 1 1
SetNyquistZone 0 2 0 1
SetNyquistZone 0 2 1 1
SetNyquistZone 0 3 0 1
SetNyquistZone 0 3 1 1
Fullscreen soc_model_rfdc_setup.txt Download 
%%
% This script was auto-generated from SoC Builder on 22-Nov-2025 17:20:31 
% for the model 'soc_model'.
% Edit this script as necessary to conform to your design specification or 
% settings.

%% Instantiate object and basic settings
IPAddr = '169.254.0.2';
rfobj = soc.RFDataConverter('ZU48DR',IPAddr);

rfobj.MTSConfigure = true;

PLLSrc = 'Internal';
ReferenceClock = 245.76; % MHz 
ADCSamplingRate = 3932.16; % MHz 
DACSamplingRate = 3932.16; % MHz 
DecimationFactor = 2;
InterpolationFactor = 2;
adcFineMixMode = true; % if set to false use coarse mixer 
dacFineMixMode = true; % if set to false use coarse mixer 


%% User FPGA-logic settings
rfobj.FPGASamplesPerClock = 8;
rfobj.ConverterClockRatio = 1;

% Check if FPGA clock-rate exceeds timing used during synthesis
FPGAClockRate = ADCSamplingRate/DecimationFactor/rfobj.FPGASamplesPerClock;
if FPGAClockRate > 245.76
    warning(['Selected FPGA rate %3.3f MHz exceeds the timing that was used ' ...
        'during synthesis (%3.3f MHz) for this design! Timing failures may ' ...
        'occur which can lead to unexpected behavior. Re-synthesizing your ' ...
        'design may be required to achieve faster rates.'],...
        FPGAClockRate, 245.76);
end

%% Establish TCP/IP connection
setup(rfobj);

%% Set External Clocking Options
% Set required clocks for MTS
rfobj.LMKClkSelect = 'SYSREF';
rfobj.configureLMXPLL(ReferenceClock);



%% Setup ADC/DAC Tile sampling and PLL rates
for TileId = 0:(rfobj.TotalADCTiles-1)
	rfobj.configureADCTile(TileId,PLLSrc,ReferenceClock,ADCSamplingRate);
    for ChId = 0:(rfobj.ADCChannelsPerTile-1)
		rfobj.configureADCChannel(TileId,ChId,DecimationFactor);
    end
end

for TileId = 0:(rfobj.TotalDACTiles-1)
    rfobj.configureDACTile(TileId,PLLSrc,ReferenceClock,DACSamplingRate);
    for ChId = 0:(rfobj.DACChannelsPerTile-1)        
		rfobj.configureDACChannel(TileId,ChId,InterpolationFactor,'DUCMode','FullNyquistDUC');        
    end
end

%% ADC IQ mode settings 

ADC_DDC_LO = [-1250 -1250 -1250 -1250 -1250 -1250 -1250 -1250]; 
ADC_MixingScale = '1';
ADC_MixerPhase = [0 0 0 0 0 0 0 0];

if rfobj.MTSConfigure
    EventMode = 'Sysref';
else   
    EventMode = 'Tile';
end

for TileId = 0:(rfobj.TotalADCTiles-1)
    for ChId = 0:(rfobj.ADCChannelsPerTile-1)           
        if adcFineMixMode %Fine Mixing Mode
            chIndx = ChId + 1 + rfobj.ADCChannelsPerTile*TileId; % one-based index
			configureADCMixer(rfobj, TileId, ChId, 'Fine', ADC_DDC_LO(chIndx), EventMode, ADC_MixerPhase(chIndx), ADC_MixingScale); 
        else %Coarse Mixing Mode
			configureADCMixer(rfobj, TileId, ChId, 'Coarse', '-Fs/4', EventMode, ADC_MixerPhase, ADC_MixingScale); 
        end
    end
end

%% DAC IQ mode settings 

DAC_DDC_LO = [1250 1250 1250 1250 1250 1250 1250 1250];
DAC_MixingScale = '1';
DAC_MixerPhase = [0 0 0 0 0 0 0 0];

if rfobj.MTSConfigure
    EventMode = 'Sysref';
else   
    EventMode = 'Immediate';
end

for TileId = 0:(rfobj.TotalDACTiles-1)
    for ChId = 0:(rfobj.DACChannelsPerTile-1) 
        if dacFineMixMode %Fine Mixing Mode
            chIndx = ChId + 1 + rfobj.DACChannelsPerTile*TileId; % one-based index
            configureDACMixer(rfobj, TileId, ChId, 'Fine', DAC_DDC_LO(chIndx), EventMode, DAC_MixerPhase(chIndx), DAC_MixingScale);
        else %Coarse Mixing Mode
            configureDACMixer(rfobj, TileId, ChId, 'Coarse', 'Fs/4', EventMode, DAC_MixerPhase, ADC_MixingScale);
        end
    end

end




%% Apply settings to RFTool
applyConfiguration(rfobj);

applyNyquistZone(rfobj);



%% Perform MTS capture
rfobj.enableMTS();



%% Disconnect and clear system object
release(rfobj);

  • +1

    Hi, You did not specify which tools and versions you are using.  But it looks like you are using MathWorks SoC Builder for RFSoC?  MathWorks is directly repsonsible for that tool.  Avnet created and maintains a related product: HDL Coder for the RFSoC ZCU208.

    Some of the code is actually the same between these 2 products, I am uncertain if the issue you are seeing is common to both or unique to just SoC Builder.  A guess would be it generated the init script in error possibly for the ZCU216, or you somehow selected the ZCU216 (but yes I can see the ZCU208's ZU48DR in the m-script).  The ZCU111, ZCU216, ZCU208 all have somewhat different numbers of and indicies for the converters within the different numbers of tiles.  In R2025a there was another change, they enabled support for 2 different Vivado, PetaLinux, RFTool and xrfdc libraries, maybe something got out of sync there?

    If you have an account with MathWorks you might want to reach out to them about this?

    Kind regards

  • 0 in reply to lightcollector

    Hi, thank you for your response, and I apologize for not including the tool details in my previous message.

    Here is the complete list of tools and versions I am currently using:

    Vivado ML Edition: 2023.1

    ===============================

    MATLAB: R2024b

    Toolboxes and Add-ons:

    Simulink: 24.2

    Communications Toolbox: 24.2

    Signal Processing Toolbox: 24.2

    DSP System Toolbox: 24.2

    Fixed-Point Designer: 24.2

    Wireless HDL Toolbox: 24.2

    SoC Blockset Support Package for AMD FPGA and SoC Devices: 24.2.1

    SoC Blockset: 24.2

    DSP HDL Toolbox: 24.2

    Embedded Coder: 24.2

    Embedded Coder Support Package for AMD SoC Devices: 24.2.11

    Embedded Coder Support Package for ARM Cortex-A Processors: 24.2.1

    HDL Coder: 24.2

    HDL Coder Support Package for Xilinx FPGA and SoC Devices: 24.2.1

    HDL Verifier: 24.2

    HDL Verifier Support Package for AMD FPGA and SoC Devices: 24.2.10

    RFSoC Explorer Toolbox: 3.3.0

    The configuration files were generated automatically following the HDL Coder IP Core Generation workflow, using the "Generic design with I/Q DAC/ADC and real-time interfaces" reference design.

    I managed to temporarily bypass the issue by manually editing the RF_init.cfg file to remove the erroneous lines. With this modification, the board boot sequence now appears to execute correctly. I verified this by measuring the relative phase shift between two tones at the DAC output. The phase shift remains consistent across multiple reboots.

    While this workaround solves the boot-up configuration, the generated MATLAB script is still unusable. Consequently, I am unable to use the script for runtime reconfiguration of the converters.

    Kind regards

  • 0 in reply to Alessio_

    Hi, Thanks for some more details.  But which product are you using?  SoC Builder for RFSoC ZCU208 or HDL Coder for RFSoC ZCU208?  They are related and do share some code but many underlying parts are different, it's critical to know.  The debug you first posted seems to indicate you are using SoC Builder for the ZCU208 but you also indicate you've installed RFSoC Explorer which installs HDL Coder for the ZCU208.  They can co-exist on the same PC too but there have been bugs before in the past with both of them installed (I am saying that in general and not suggesting that is your precise issue here).

    And if I missed some detail in your posts here that make it clear which, I apologize, but I can't tell yet from what I see.

    Thank you

  • 0 in reply to lightcollector

    Hi, apologies if I wasn't clear in my previous message.

    I am following the procedure outlined here https://rfsoc-hdlcoder.readthedocs.io/en/latest/zcu208.html.

  • 0 in reply to Alessio_

    Hi Alessio, But the link to the instructions you posted doesn't match up with the soc_model_rfdc_setup.txt source code you posted.  The latter indicates you are using SoC Builder.

    The example .m files etc. in the rfsoc hdlcoder for the ZCU208 read the docs link do not have that text in them.  All of them including the MTS example design are generated from a different set of tools and were generated with older versions of Matlab tools but they continue to work with R2025a for the ZCU208.

    For example in the header of the HDL Coder for ZCU208 MTS example, ADC_DAC_8x8_IQ_MTS_Capture_setup_rfsoc.m has:

    % This script was auto-generated from the HDL Coder Workflow Advisor for the ZCU111 and ZCU216
    % Edit this script as necessary to conform to your design specification or settings

    Another clue is that you said you are using 2023.1 AMD tools, the intructions in the read the docs link clearly state you must use 2020.2 Vivado tools for HDL Coder for the ZCU208.

    It is my opinion that you are using a mix of the 2 tools, perhaps some of the instructions for HDL Coder but are using the SoC Builder for ZCU208 tools to create the examples.  All that said, there still might be a legitimate issue with the SoC Builder workflow for the ZCU208.  I currently do not have a convenient means to work through the SoC Builder workflow.

    This forum is for HDL Coder for the ZCU208 AMD development board.  But with all of the tools you have, it seems reasonable to conclude you have access to MathWorks support, you should also try to reach out to them.  And we will also request they they take a look at the issue you posted, but this isn't the best place to get support for SoC Builder for RFSoC devices.

    Thank you

  • 0 in reply to lightcollector

    I spoke with MathWorks directly today about your issue.  They requested you file an issue with them.  Here is the generic link:  https://www.mathworks.com/support/contact_us.html?s_tid=hp_ff_s_support

    There is an RFSoC system object that bridges the Matlab m-code to the remote target's API that controls the data converters.  It is likely there is either a direct bug in the rfsoc system object or something to do with using parts of SoC Builder for RFSoC and HDL Coder for RFSoC on the same setup.  The log you posted indicates that somehow the conveter Matlab indicies are incorrect for the ZCU208.

    You pasted the correct link for HDL Coder for the ZCU208 instructions, the MTS Example is in the zip file that the instructions link to: https://github.com/AvnetDev/hdlcoder-zcu208-zip/releases/download/v1.0.5/zcu208-hdlcoder.zip 

    And here is the link for SoC Blockset / Builder for the RFSoC dev boards MTS example: https://www.mathworks.com/help/soc/ug/multi-tile-synchronization-using-rfsoc-device.html

    Finally, would just comment that if it is the system object, even for HDL Coder for the ZCU208, MathWorks owns that portion and contols its distribution and release.  I am very confident they will respond to your issue if you request support.