RFSoC Boards - Recent Threads

ZCU208 2024b and 2025a

drew314 — Thu, 19 Feb 2026 15:54:19 GMT

I am trying to generate HDL and SW project for ZCU208 IQ example.

I have matlab 2024b and 2025a installed.

Running though the HDL workflow advisor with unmodified slx, I get this error for both the Real and IQ examples. I get the error both in 2024b and 2025a.

I have the IIO stream blocks in my simulink library, but do not know what to do with them.

Note No driver block was generated for port(s) "Tile0 ADC Ch0 Data" mapped to interface "Tile0 ADC Ch0 Data" in the software interface model.

Note No driver block was generated for port(s) "Tile0 ADC Ch0 Valid" mapped to interface "Tile0 ADC Ch0 Valid" in the software interface model.

Note No driver block was generated for port(s) "Tile0 DAC Ch0 Data" mapped to interface "Tile0 DAC Ch0 Data" in the software interface model.

Note No driver block was generated for port(s) "Tile0 DAC Ch0 Valid" mapped to interface "Tile0 DAC Ch0 Valid" in the software interface model.

Warning The AXI4-Stream IIO driver block cannot be automatically generated in the software interface model when a scalar port, "MM2S_Data", is mapped to AXI4-Stream interface "AXI4-Stream DMA". Before you generate code from the software interface model, add the AXI4-Stream IIO driver block from "Simulink Library Browser" -> "Embedded Coder Support Package for AMD SoC Devices" library, change "MM2S_Data" into a vector, and connect the vector port to the driver block.

Warning The AXI4-Stream IIO driver block cannot be automatically generated in the software interface model when a scalar port, "S2MM_Data", is mapped to AXI4-Stream interface "AXI4-Stream DMA". Before you generate code from the software interface model, add the AXI4-Stream IIO driver block from "Simulink Library Browser" -> "Embedded Coder Support Package for AMD SoC Devices" library, change "S2MM_Data" into a vector, and connect the vector port to the driver block.

Note No driver was generated for port(s) "Tile0 ADC Ch0 Data" mapped to interface "Tile0 ADC Ch0 Data" in the host interface script.

Note No driver was generated for port(s) "Tile0 ADC Ch0 Valid" mapped to interface "Tile0 ADC Ch0 Valid" in the host interface script.

Note No driver was generated for port(s) "Tile0 DAC Ch0 Data" mapped to interface "Tile0 DAC Ch0 Data" in the host interface script.

Note No driver was generated for port(s) "Tile0 DAC Ch0 Valid" mapped to interface "Tile0 DAC Ch0 Valid" in the host interface script.

Failed Generate Software Interface.

Generating new Zynq Software Interface model: gm_rfsocADCCapture_interface

SoC Blockset and SoC Blockset Support Package for AMD FPGA and SoC Devices are required to generate software interface model.

Zynq Software Interface model generation complete.

Generating new Xilinx Host Interface script: gs_rfsocADCCapture_interface.m

Xilinx Host Interface script generation complete.

ZCU208 MTS error in RF_init.cfg

Alessio_ — Sun, 23 Nov 2025 09:29:20 GMT

Hi,
I’m encountering an issue while implementing the MTS feature on the ZCU208 using MATLAB. From what I can see in the RF_init.cfg file, there seems to be a configuration problem. The initial setup appears to be correct and the MTS function starts properly, but afterwards other functions are called with incorrect arguments. Specifically, ResetNCOPhase is being applied to DACs 0 and 1, whereas on the ZCU208 the active DACs are 0 and 2. As a result, the log reports an error stating digital datapath 1 is not active. Should I manually modify the init file, or is possible to fix the problem in the MATLAB script instead?

community.element14.com/.../RF_5F00_Init.txt community.element14.com/.../soc_5F00_model_5F00_rfdc_5F00_setup.txt

Matlab R2025 Compatibility Issue with RFSoC ZCU208 from AMD/Xilinx

Saeedk74 — Wed, 19 Nov 2025 04:53:25 GMT

I am having issues communicating with RFSoC ZCU208 from AMD/Xilinx using Matlab R2025a, but I have no issues with R2024b! The issue seems to be related to the AVNET RFSoC Explorer toolbox not supported in R2025a. Appreciate it any ressonse on this.

Technical data for the XRF8 RFSoC Gen3 System-on-Module

Salemuae — Tue, 21 Oct 2025 06:24:05 GMT

Hello, I am evaluating the XRF8 RFSoC Gen3 System-on-Module for integration into a multi-channel 5G signal processing platform. I am interested in purchasing the complete kit, including:
- XRF8 SOM (ZU47DR or ZU48DR)
- Carrier Board
- Avalon Suite

To proc

How to enable both DDR4s on ZCU208 RFSoC Simulink models where I like to have both ADC and DACs streaming to/from separate DDR4?

Saeedk74 — Mon, 02 Jun 2025 04:50:20 GMT

The examples provided for ADC/DAC with DDR4 interface only support one DDR4. I have modified them so I could simultaneously capture ADC samples to one DDR4 and stream DAC samples from another DDR4. I modified the reference designs and made sure that the HDL workflow advisor detects the changes in the plugin_rd.m. I also manually added 2 AXI4Master in plungin_rd.com. Everything is good till I make the Vivado project and it fails there! The failure is related to connecting the AXI to DDR4 MIG! I did everything you could possibly imagine, but no luck! That would be great if someone could provide instructions which work! Appreciate any response.

Problems with the RFSoC Explorer and the resulting signal

rcarli — Fri, 26 Jul 2024 08:35:23 GMT

Hey,

I want to use the RFSoC to investigate the effect of different filters on the resulting analog signal. For this I use a DAC-ADC loop and an external signal analyzer. For this I use the RFSoc Explorer. This also works so far. However, I have the following problems:

When transferring the waveform from the Wireless Waveform Generator of Matlab, the following error message appears:

"Connected to RFTool
Board IP address 169.254.0.2
Error in executing callback registered with ViewModel:
Error using wwfg_callback
Unrecognized field name "pCurrentWaveformType"."

Is there a way to fix this?

The import from simulink does not work either. Here i get the message: "Unrecogized signal type"

Becouse of the error i exported the waveform as a Matlab script and generated the variable “Waveform.mat” with the complex data signal. According to the Matlab plot, this signal should have a bandwidth of about 1MHz. However, when I load the signal into the RFSoc Explorer and transfer it to the hardware, I get a bandwidth of approx. 40MHz. The same problem i get with my generated signals from Simulink, which I save as a complex data array as a .mat file.

The bandwidth should be similar to the simulated result, or am I forgetting something here? Is it possibly also due to the waveform read in?

My setup:

Xilinx ZCU208 RFSoC Gen 3
HW-XM655 Balun Card
Matlab 2023b
Avnet RFSoC Explorer 3.0.0 (with 3.1 i cant find the ZCU208 Board at the HDL Worklow Advisor)
"avnet_rfsocX_zcu208es1_boot_v1_1"- file
Keysight EXA Signal Analyzer

{gallery}My Gallery Title
Settings RF Explorer
Settings for Simple Waveform to test

{gallery}My Gallery Title

Settings RF Explorer

Settings for Simple Waveform to test

Thank you in advance and best regards

RFSoC ZCU 208 whit Matlab HDL Coder - Getting Startet trouble

rcarli — Wed, 03 Jul 2024 11:10:45 GMT

Hi there.

I went through the "Getting Started with HDL Coder for the Xilinx ZCU208 RFSoC Gen 3 development board" (rfsoc-hdlcoder.readthedocs.io/.../zcu208.html) to test and familiarize myself with the functionality.

It worked fine up to step 12. But at the HDL Worklow Advisor at "4.2 Generate Software Interface" it gets stuck. This is because the SoC Blockset Toolbox is required. Do I really need this toolbox, is this a new requirement, or is something else wrong?
According to the "Getting Started ... - Required Software" section, there is no need.

I also get further warnings and notes that something cannot be generated and should be changed manual, is this possibly due to the version difference between the creation of the model and my version? Or can i ignore them?

I am using:

Xilinx ZCU208 RFSoC Gen 3
Matlab 2023b
Vivado 2020.2
Avnet RFSoC Explorer 3.0.0
Fixed Point Designer Toolbox v. 23.2
HDL Coder v. 23.2.0
HDL Coder Support Package (FPGA Boards, RFSoCDevices, Zynq Platform) v. 23.2.0
DSP System Toolbox v.23.2
The unchanged Simulink Model out of the example folder -> rfsocADCCapture

Thank you in advance and best regards

Zync 7020 com code working fine but somehow not showing the results i wish .

trickntreat — Fri, 22 Mar 2024 20:47:39 GMT

I wrote this script for my led to blink . It is connected to MIO47 .

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "xgpiops.h"
#include "xparameters.h"

XGpioPs led;
XGpioPs_Config *led_config;

void init(){
	int status;
	led_config = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);
	status = XGpioPs_CfgInitialize(&led, led_config, led_config->BaseAddr);
	if(status == XST_SUCCESS)
		xil_printf("Device Init Successful\n");
	else
		xil_printf("Device Init Failed\n");

}


int main()
{
    init_platform();
    init();
    xil_printf("Starting GPIO MIO LED TEST\n");
    XGpioPs_SetDirectionPin(&led, 47, 1);
    XGpioPs_SetOutputEnablePin(&led, 47, 1);

    while(1){
    	XGpioPs_WritePin(&led, 47, 1);
    	sleep(1);
    	XGpioPs_WritePin(&led, 47, 0);
    	sleep(1);

    }



    cleanup_platform();
    return 0;
}

It doesn't blink neither it shows any errors .

I then went on to check if i can print hello world even . It doesn't even display that . Can someone help ?

Tried connecting different COM ports and all . But still no luck

About status LEDs of RFSoC ZCU208 board

Hiroaki — Wed, 13 Mar 2024 09:51:12 GMT

Getting started with HDL Coder for the Xilinx ZCU208 RFSoC Gen 3 development board — hdlcoder-docs v1.0.0 documentation (rfsoc-hdlcoder.readthedocs.io)
Follow step8, I inserted SD card. But, LED of "DS2" turned on red in RFSoC ZCU208 board and it did not turn green over time. I think there is a problem with the operation of the FPGA, but I don't know the cause.

If anyone knows the cause or solution, please let me know.

Avnet XRF8 Gen3 SOM Thermal Requirements

jake8jensen — Mon, 11 Mar 2024 15:33:04 GMT

I’m reaching out to inquire about the thermal management requirements of the XRF8 Gen3 SOM. We plan to use the XRF Heatsink V2 (AES-XRF-HEATSINK-V2) with the AES-XRF-HEATSINK-V2-FAN. However, we intend to operate at altitudes up to 20kft where there is a reduction in convective cooling. What is the maximum allowable heatsink temperature that will insure SOM performance?

RFSoC ZCU208 HDL Coder Support in MATLAB/Simulink

jgabaldo55 — Thu, 09 Nov 2023 22:34:40 GMT

I have an RFSoC ZCU208 board. I went through the example found here:

Getting started with HDL Coder for the Xilinx ZCU208 RFSoC Gen 3 development board — hdlcoder-docs v1.0.0 documentation (rfsoc-hdlcoder.readthedocs.io)

I was able to successfully complete steps 1 - 10 and program the fpga with the example bitstream (from the adcdemo example) generated from the attached MATLAB/Simulink files. I then proceeded to try and rebuild the adcdemo example using the "HDL Workflow Advisor" in Simulink so that I can see the process from start to finish. While in the tool, on the step "Set Target Device and Synthesis Tool", I set "Target Workflow" to "IP Core Generation" but when I went to set "Target Platform", it did not give me the option for "Xilinx Zynq Ultrascale+ RFSoC ZCU208 Evaluation Board" like it does in the example. I am wondering why that is. The only boards that are available of the "Xilinx Zynq Ultrascale+ RFSoC" type are the ZCU111 and ZCU216.

Has anyone else experienced this? I am wondering if the ZCU208 support was removed from the Support Packages for whatever reason? I downloaded the correct support packages, which include the "HDL Coder Support Package for Xilinx RFSoC Devices" and the "HDL Coder Support Package for Zynq." If anyone has any suggestions or insights, it would be greatly appreciated.

Thank you.

ZCU208 evaluation board with otava DTRX2

Saheed — Wed, 25 Oct 2023 17:45:24 GMT

Hi,

I have two questions about the ZCU208 Evaluation board.

1. How many total analog IF ports the ZCU208 supports?

2. The 'MMWave_Radio_Development_Kit_Product_Brief' from Otava mentions the need for an external image filter. Can you tell me what that filter is and why it is required?

Otava DTRX2 mmWave transceiver - what are the allowable bandwidths?

mbrown — Mon, 05 Jun 2023 15:05:10 GMT

What are the range of allowable bandwidths that can be up/down-converted, and if there is a relationship between bandwidth and possible RF/IF frequencies, what is that relationship?

CLK104 PLL Lock

dchien — Fri, 05 May 2023 09:02:40 GMT

The CLK104 clock board on my ZCU208 evaluation board does not have all PLL lock LEDs on. The clock distribution PLL (U2) has its lock LED (DS1) on, but the DAC PLL (U7) has its LED (DS3) off and the ADC PLL (U5) has its lock LED (DS2) off. Do I have a defective CLK104 board? What can cause the ADC and DAC PLLs not locking (LEDs off)?

Thanks!

Understanding Nyquist Zones in Avnet RFSoC Explorer for MATLAB

LucLanglois — Wed, 26 Apr 2023 22:52:36 GMT

AMD-Xilinx documentation is extensive. Zynq UltraScale+ RFSoC is a complex device. It can be daunting searching through docs for guidance on a topic such as managing Nyquist zones with RFSoC complex mixer https://docs.xilinx.com/r/en-US/pg269-rf-data-converter/NCO-Frequency-Conversion

Avnet RFSoC Explorer MATLAB app manages Nyquist zones in the RFSoC ADC DDC. I created a short video to help unravel this topic.

players.brightcove.net/.../index.html

Avnet RFSoC Explorer Failed to Connect to Target

dchien — Sat, 01 Apr 2023 05:43:14 GMT

Several months ago I was able to run Avnet RFSoC Explorer 2.2 on ZCU208 evaluation board. I tried to run the same application today and it failed to connect to target. Below is a history from my command window. I then tried to ping the board's IP address and the board was respoding to my ping. What is wrong with my setup?

Thanks.

---------

Prepending following Xilinx Vivado path(s) to the system path:
C:\Xilinx\Vivado\2020.2\bin
Target board [3] ZCU208
Opening Avnet RFSoC Explorer...
Failed to connect to target at 169.254.184.100
>> !ping 169.254.184.100

Pinging 169.254.184.100 with 32 bytes of data:
Reply from 169.254.184.100: bytes=32 time=1ms TTL=64
Reply from 169.254.184.100: bytes=32 time=1ms TTL=64
Reply from 169.254.184.100: bytes=32 time=1ms TTL=64
Reply from 169.254.184.100: bytes=32 time=1ms TTL=64

Ping statistics for 169.254.184.100:
Packets: Sent = 4, Received = 4, Lost = 0 (0% loss),
Approximate round trip times in milli-seconds:
Minimum = 1ms, Maximum = 1ms, Average = 1ms
>>

Warning- TX PLL not locked, Please double check hardware setup

johnj0806 — Sat, 13 Aug 2022 01:19:34 GMT

I am using the Avnet RFSOC Explorer for MATLAB to interface with ZCU208+DTRX2. I am following the setup instruction. Whenever I click the TX Power UP, I get the error "Warning- TX PLL not locked, Please double check hardware setup". I am not sure what I am doing wrong as I have verified that I am outputting 122.88 MHz ref from CLK104 module. Any ideas?

RFSoC rftool console command argument.

khabnl — Thu, 23 Jun 2022 02:24:54 GMT

Hello,

I am attempting to load the “RF_Init.cfg” file manually using “rftool” console command.

The ZCU208 Linux boot-up automatically loads the “/mnt/hdlcoder_rd/RF_Init.cfg” file and initializes it.

If I delete the “/mnt/hdlcoder_rd/RF_Init.cfg” file then the console shows an error message.

rf_init: Could not locate /mnt/hdlcoder_rd/RF_Init.cfg ! Exiting...

Does anyone know what rftool options are for loading user configuration files at the console?

zynqrf> rftool

Version number; 2.4

Board version ZCU208

RFCLK v1.4

RFCLK v1.4 Init Done
starting server...
starting data server...
IP Address of the board: 192.168.1.101
Server Init Done

Thanks,

No reference designs exist for selected target:ZCU208

khabnl — Thu, 16 Jun 2022 14:13:04 GMT

Hello,

I am trying to test zcu208 example from https://rfsoc-hdlcoder.readthedocs.io/en/latest/zcu208.html

Step 1: download zcu208-hdlcoder.zip

Step 2: extract zip files and install at Matlab 2021.b

>> installhdl208

Info: to complete the network setup, enter your IP settings in the interfaces file.

Info: the interfaces file should now be open in the Matlab text editor.

Step 3:

I opened one example, rfsocADCCapture using Matlab 2021.b and HDL Workflow adviser and selected the target device.

DAC sampling frequency over 7 Gsps with ZCU208

McG — Thu, 05 May 2022 22:59:54 GMT

Hello everyone,

I'm working with a ZCU208 board by using the matlab/simulink board support provided at this link:

https://rfsoc-hdlcoder.readthedocs.io/en/latest/zcu208.html

All the examples work fine and I'm capable to modify the templates for my purposes without particular problems.

The only issue is related to when I try to set the sampling rate of the DACs over 7 Gsps, namely 8.6 GHz.

I receive the error: Maximum DAC frequency when using FullNyquistDUC is 7000 MHz

Of course, I'm not using Fully Nyquist mode, but I set the IMR filter in High Pass mode as depicted in the screenshot below:

It seems that the problem is connected with soc.RFDataConverter object provided by Xilinx, but I'm not sure.

Did anyone have the same problem or is able to replicate it?

Regards

XRF16™︎ RFSoC System-on-Module

msabatino — Mon, 11 Apr 2022 20:22:36 GMT

XRF16™ RFSoC System-on-Module
Interested with further details of Avnet AES-XRF16-ZU49-G and carrier board that are not on your website. In particular
1. Detailed mechanical dimensional drawings of the assembly in print or ideally 2 or 3 dimensional CAD files
2. Information on the heat dissipation of the assembly. In particular heat sink contact areas and corresponding thermal dissipation.

Your response to this request is greatly appreciated.

Otava DTRX2 mmWave Radio Card API Information

mihoaut — Thu, 27 Jan 2022 14:14:13 GMT

Hello,

we bought a Xilinx RFSoC Gen 3 Kit for mmWave consisting of a Otava DTRX2 mmWave Radio Card and a Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit.

Currently we are in the process of building our own pynq based developer enviroment which perfeclty fits our individual needs.

Slowly but surely, our progress is limited by the fact, that there is no information about how the communication of the ZCU208 with the DTRX2 is taking place.

Can you provide information/documentation/drivers/libraries/modules, or whatever needed, to be able to implement this communication in our own pynq project?

Thank you.

Best regards.

Otava DTRX2 mmWave Radio Card for Xilinx RFSoC ZCU208 Evaluation Kit

migration.user — Thu, 07 Oct 2021 11:41:09 GMT

Hi,

i have sent two Emails, for my question. The first forwarded me the second, and for the second in got no reply yet (Case Number 02095097). So I try to ask here:

Hi,

my institute ant the Johannes Kepler University Linz, Austria recently bought the "Xilinx RFSoC Gen 3 Kit for mmWave”.

Now as we started to get to know the board with the Avnet RFSoC Explorer, we now want to move on and use the Xiliinx Vivado Desing Suit, to work with the board.

Therefore we need additional information about the “Otava DTRX2 mmWave Radio Card for Xilinx RFSoC ZCU208 Evaluation Kit”. Neither on the Otava, nor on your site I was able to find some detailed technical data, about how to access, configure and use this daughter board. So please can you provide this data ?

Thank you!

Best Regards.