RFSoC Boards - Recent Threads

ZCU208 2024b and 2025a

drew314 — Thu, 19 Feb 2026 15:54:19 GMT

I am trying to generate HDL and SW project for ZCU208 IQ example.

I have matlab 2024b and 2025a installed.

Running though the HDL workflow advisor with unmodified slx, I get this error for both the Real and IQ examples. I get the error both in 2024b and 2025a.

I have the IIO stream blocks in my simulink library, but do not know what to do with them.

Note No driver block was generated for port(s) "Tile0 ADC Ch0 Data" mapped to interface "Tile0 ADC Ch0 Data" in the software interface model.

Note No driver block was generated for port(s) "Tile0 ADC Ch0 Valid" mapped to interface "Tile0 ADC Ch0 Valid" in the software interface model.

Note No driver block was generated for port(s) "Tile0 DAC Ch0 Data" mapped to interface "Tile0 DAC Ch0 Data" in the software interface model.

Note No driver block was generated for port(s) "Tile0 DAC Ch0 Valid" mapped to interface "Tile0 DAC Ch0 Valid" in the software interface model.

Warning The AXI4-Stream IIO driver block cannot be automatically generated in the software interface model when a scalar port, "MM2S_Data", is mapped to AXI4-Stream interface "AXI4-Stream DMA". Before you generate code from the software interface model, add the AXI4-Stream IIO driver block from "Simulink Library Browser" -> "Embedded Coder Support Package for AMD SoC Devices" library, change "MM2S_Data" into a vector, and connect the vector port to the driver block.

Warning The AXI4-Stream IIO driver block cannot be automatically generated in the software interface model when a scalar port, "S2MM_Data", is mapped to AXI4-Stream interface "AXI4-Stream DMA". Before you generate code from the software interface model, add the AXI4-Stream IIO driver block from "Simulink Library Browser" -> "Embedded Coder Support Package for AMD SoC Devices" library, change "S2MM_Data" into a vector, and connect the vector port to the driver block.

Note No driver was generated for port(s) "Tile0 ADC Ch0 Data" mapped to interface "Tile0 ADC Ch0 Data" in the host interface script.

Note No driver was generated for port(s) "Tile0 ADC Ch0 Valid" mapped to interface "Tile0 ADC Ch0 Valid" in the host interface script.

Note No driver was generated for port(s) "Tile0 DAC Ch0 Data" mapped to interface "Tile0 DAC Ch0 Data" in the host interface script.

Note No driver was generated for port(s) "Tile0 DAC Ch0 Valid" mapped to interface "Tile0 DAC Ch0 Valid" in the host interface script.

Failed Generate Software Interface.

Generating new Zynq Software Interface model: gm_rfsocADCCapture_interface

SoC Blockset and SoC Blockset Support Package for AMD FPGA and SoC Devices are required to generate software interface model.

Zynq Software Interface model generation complete.

Generating new Xilinx Host Interface script: gs_rfsocADCCapture_interface.m

Xilinx Host Interface script generation complete.

RE: ZCU208 2024b and 2025a

mbrown — Tue, 24 Feb 2026 19:28:05 GMT

Hello drew314 ,

Please try unchecking the "Generate Simulink Software Interface mdoel' box in step 4.2. If I recall correctly, the ADCCapture design is HDL-only.

ZCU208 MTS error in RF_init.cfg

Alessio_ — Sun, 23 Nov 2025 09:29:20 GMT

Hi,
I’m encountering an issue while implementing the MTS feature on the ZCU208 using MATLAB. From what I can see in the RF_init.cfg file, there seems to be a configuration problem. The initial setup appears to be correct and the MTS function starts properly, but afterwards other functions are called with incorrect arguments. Specifically, ResetNCOPhase is being applied to DACs 0 and 1, whereas on the ZCU208 the active DACs are 0 and 2. As a result, the log reports an error stating digital datapath 1 is not active. Should I manually modify the init file, or is possible to fix the problem in the MATLAB script instead?

[View:/cfs-file/__key/communityserver-discussions-components-files/322/RF_5F00_Init.txt:640:360][View:/cfs-file/__key/communityserver-discussions-components-files/322/soc_5F00_model_5F00_rfdc_5F00_setup.txt:640:360]

RE: ZCU208 MTS error in RF_init.cfg

lightcollector — Thu, 18 Dec 2025 01:30:39 GMT

I spoke with MathWorks directly today about your issue. They requested you file an issue with them. Here is the generic link: https://www.mathworks.com/support/contact_us.html?s_tid=hp_ff_s_support

There is an RFSoC system object that bridges the Matlab m-code to the remote target's API that controls the data converters. It is likely there is either a direct bug in the rfsoc system object or something to do with using parts of SoC Builder for RFSoC and HDL Coder for RFSoC on the same setup. The log you posted indicates that somehow the conveter Matlab indicies are incorrect for the ZCU208.

You pasted the correct link for HDL Coder for the ZCU208 instructions, the MTS Example is in the zip file that the instructions link to: https://github.com/AvnetDev/hdlcoder-zcu208-zip/releases/download/v1.0.5/zcu208-hdlcoder.zip

And here is the link for SoC Blockset / Builder for the RFSoC dev boards MTS example: https://www.mathworks.com/help/soc/ug/multi-tile-synchronization-using-rfsoc-device.html

Finally, would just comment that if it is the system object, even for HDL Coder for the ZCU208, MathWorks owns that portion and contols its distribution and release. I am very confident they will respond to your issue if you request support.

RE: ZCU208 MTS error in RF_init.cfg

lightcollector — Tue, 16 Dec 2025 04:32:58 GMT

Hi Alessio, But the link to the instructions you posted doesn't match up with the soc_model_rfdc_setup.txt source code you posted. The latter indicates you are using SoC Builder.

The example .m files etc. in the rfsoc hdlcoder for the ZCU208 read the docs link do not have that text in them. All of them including the MTS example design are generated from a different set of tools and were generated with older versions of Matlab tools but they continue to work with R2025a for the ZCU208.

For example in the header of the HDL Coder for ZCU208 MTS example, ADC_DAC_8x8_IQ_MTS_Capture_setup_rfsoc.m has:

% This script was auto-generated from the HDL Coder Workflow Advisor for the ZCU111 and ZCU216
% Edit this script as necessary to conform to your design specification or settings

Another clue is that you said you are using 2023.1 AMD tools, the intructions in the read the docs link clearly state you must use 2020.2 Vivado tools for HDL Coder for the ZCU208.

It is my opinion that you are using a mix of the 2 tools, perhaps some of the instructions for HDL Coder but are using the SoC Builder for ZCU208 tools to create the examples. All that said, there still might be a legitimate issue with the SoC Builder workflow for the ZCU208. I currently do not have a convenient means to work through the SoC Builder workflow.

This forum is for HDL Coder for the ZCU208 AMD development board. But with all of the tools you have, it seems reasonable to conclude you have access to MathWorks support, you should also try to reach out to them. And we will also request they they take a look at the issue you posted, but this isn't the best place to get support for SoC Builder for RFSoC devices.

Thank you

RE: ZCU208 MTS error in RF_init.cfg

Alessio_ — Mon, 15 Dec 2025 08:41:56 GMT

Hi, apologies if I wasn't clear in my previous message.

I am following the procedure outlined here https://rfsoc-hdlcoder.readthedocs.io/en/latest/zcu208.html.

RE: ZCU208 MTS error in RF_init.cfg

lightcollector — Mon, 15 Dec 2025 03:24:41 GMT

Hi, Thanks for some more details. But which product are you using? SoC Builder for RFSoC ZCU208 or HDL Coder for RFSoC ZCU208? They are related and do share some code but many underlying parts are different, it's critical to know. The debug you first posted seems to indicate you are using SoC Builder for the ZCU208 but you also indicate you've installed RFSoC Explorer which installs HDL Coder for the ZCU208. They can co-exist on the same PC too but there have been bugs before in the past with both of them installed (I am saying that in general and not suggesting that is your precise issue here).

And if I missed some detail in your posts here that make it clear which, I apologize, but I can't tell yet from what I see.

Thank you

RE: ZCU208 MTS error in RF_init.cfg

Alessio_ — Fri, 12 Dec 2025 08:15:59 GMT

Hi, thank you for your response, and I apologize for not including the tool details in my previous message.

Here is the complete list of tools and versions I am currently using:

Vivado ML Edition: 2023.1

===============================

MATLAB: R2024b

Toolboxes and Add-ons:

Simulink: 24.2

Communications Toolbox: 24.2

Signal Processing Toolbox: 24.2

DSP System Toolbox: 24.2

Fixed-Point Designer: 24.2

Wireless HDL Toolbox: 24.2

SoC Blockset Support Package for AMD FPGA and SoC Devices: 24.2.1

SoC Blockset: 24.2

DSP HDL Toolbox: 24.2

Embedded Coder: 24.2

Embedded Coder Support Package for AMD SoC Devices: 24.2.11

Embedded Coder Support Package for ARM Cortex-A Processors: 24.2.1

HDL Coder: 24.2

HDL Coder Support Package for Xilinx FPGA and SoC Devices: 24.2.1

HDL Verifier: 24.2

HDL Verifier Support Package for AMD FPGA and SoC Devices: 24.2.10

RFSoC Explorer Toolbox: 3.3.0

The configuration files were generated automatically following the HDL Coder IP Core Generation workflow, using the "Generic design with I/Q DAC/ADC and real-time interfaces" reference design.

I managed to temporarily bypass the issue by manually editing the RF_init.cfg file to remove the erroneous lines. With this modification, the board boot sequence now appears to execute correctly. I verified this by measuring the relative phase shift between two tones at the DAC output. The phase shift remains consistent across multiple reboots.

While this workaround solves the boot-up configuration, the generated MATLAB script is still unusable. Consequently, I am unable to use the script for runtime reconfiguration of the converters.

Kind regards

RE: ZCU208 MTS error in RF_init.cfg

lightcollector — Fri, 05 Dec 2025 07:13:25 GMT

Hi, You did not specify which tools and versions you are using. But it looks like you are using MathWorks SoC Builder for RFSoC? MathWorks is directly repsonsible for that tool. Avnet created and maintains a related product: HDL Coder for the RFSoC ZCU208.

Some of the code is actually the same between these 2 products, I am uncertain if the issue you are seeing is common to both or unique to just SoC Builder. A guess would be it generated the init script in error possibly for the ZCU216, or you somehow selected the ZCU216 (but yes I can see the ZCU208's ZU48DR in the m-script). The ZCU111, ZCU216, ZCU208 all have somewhat different numbers of and indicies for the converters within the different numbers of tiles. In R2025a there was another change, they enabled support for 2 different Vivado, PetaLinux, RFTool and xrfdc libraries, maybe something got out of sync there?

If you have an account with MathWorks you might want to reach out to them about this?

Kind regards

RE: Matlab R2025 Compatibility Issue with RFSoC ZCU208 from AMD/Xilinx

mbrown — Mon, 24 Nov 2025 16:52:03 GMT

RFSoC Explorer v3.3.0 supports R2024b and R2025a and has been tested on both versions.As lightcollector requested, please send more details - screen shots, error messages, host PC OS version, etc. so that we can help diagnose the problem.

Thanks /Matt

Matlab R2025 Compatibility Issue with RFSoC ZCU208 from AMD/Xilinx

Saeedk74 — Wed, 19 Nov 2025 04:53:25 GMT

I am having issues communicating with RFSoC ZCU208 from AMD/Xilinx using Matlab R2025a, but I have no issues with R2024b! The issue seems to be related to the AVNET RFSoC Explorer toolbox not supported in R2025a. Appreciate it any ressonse on this.

RE: Matlab R2025 Compatibility Issue with RFSoC ZCU208 from AMD/Xilinx

lightcollector — Sat, 22 Nov 2025 08:14:52 GMT

Hi, HDL Coder for RFSoC ZCU208 does work with R2025a. Even if RFSoC Explorer says it doesn't support R2025a, I believe it will still install (adds it to the Matlab path) the plugin folder that enables the ZCU208 to work with HDL Coder.

You did not communicate any specific details of your issue, so I can only try to guess. The install instructions are a bit convoluted since we try to cover older Matlab versions as well. Please make sure you have all of the other support packages installed, and for R2025a you must install the ZCU216 board setup just as it states in the instructions. Avnet HDL Coder Support Documentation — hdlcoder-docs v1.0.0 documentation

Kind regards

Technical data for the XRF8 RFSoC Gen3 System-on-Module

Salemuae — Tue, 21 Oct 2025 06:24:05 GMT

Hello, I am evaluating the XRF8 RFSoC Gen3 System-on-Module for integration into a multi-channel 5G signal processing platform. I am interested in purchasing the complete kit, including:
- XRF8 SOM (ZU47DR or ZU48DR)
- Carrier Board
- Avalon Suite

To proc

RE: Hello, I am evaluating the XRF8 RFSoC Gen3 System-on-Module for integration into a multi-channel 5G signal processing platform. I am interested in purchasing the complete kit, including: - XRF8 SOM (ZU47DR or ZU48DR) - Carrier Board - Avalon Suite To

mbrown — Wed, 22 Oct 2025 16:33:13 GMT

Great to hear that you connected with Avnet Silica Account Mgr, Enes. I am the XRF Product Mgr. at Tria Technologies. We can probably make faster progress if we share an email thread. Please send an email to rfinfo@avnet.com and include Enes. Thanks!

/Matt

RE: Hello, I am evaluating the XRF8 RFSoC Gen3 System-on-Module for integration into a multi-channel 5G signal processing platform. I am interested in purchasing the complete kit, including: - XRF8 SOM (ZU47DR or ZU48DR) - Carrier Board - Avalon Suite To

Salemuae — Wed, 22 Oct 2025 07:49:46 GMT

Hello mbrown

Good day.

I have received an email from Enes Merter

Is it conducted by you? Do I need to contact rfinfo@avnet.com?

Thank you.

RE: Hello, I am evaluating the XRF8 RFSoC Gen3 System-on-Module for integration into a multi-channel 5G signal processing platform. I am interested in purchasing the complete kit, including: - XRF8 SOM (ZU47DR or ZU48DR) - Carrier Board - Avalon Suite To

mbrown — Tue, 21 Oct 2025 15:41:13 GMT

Hi Salemuae Please send your request to rfinfo@avnet.com and I'll assist you directly.

Thanks! /Matt

RE: Hello, I am evaluating the XRF8 RFSoC Gen3 System-on-Module for integration into a multi-channel 5G signal processing platform. I am interested in purchasing the complete kit, including: - XRF8 SOM (ZU47DR or ZU48DR) - Carrier Board - Avalon Suite To

iksevas — Tue, 21 Oct 2025 06:27:26 GMT

Do you have an Avnet sales contact in your region? If not, please send me a direct message so I can point you in the correct direction.

RE: How to enable both DDR4s on ZCU208 RFSoC Simulink models where I like to have both ADC and DACs streaming to/from separate DDR4?

lightcollector — Wed, 11 Jun 2025 22:07:02 GMT

Hi, there are various .m files and .tcl files that generate the Vivado block design. The way MathWorks designed the tool, it is not intended that an end user modify their copyrighted files. Most of the MathWorks tools, including this one are not open-source. Officially I cannot condone or support modifying MathWorks tools: legally and liability-wise you are on your own to do such.

But... none of the source code that generates the .tcl code that wires up and configures the various IPs in the Vivado block design is hidden. In addition to the ZCU208 specifics that are installed through RFSoC Explorer, MathWorks RFSoC Add-On for HDL Coder also installs various source code including a common part, as well as specifics for the ZCU111 and ZCU216 RFSoC dev boards.

Good luck!

How to enable both DDR4s on ZCU208 RFSoC Simulink models where I like to have both ADC and DACs streaming to/from separate DDR4?

Saeedk74 — Mon, 02 Jun 2025 04:50:20 GMT

The examples provided for ADC/DAC with DDR4 interface only support one DDR4. I have modified them so I could simultaneously capture ADC samples to one DDR4 and stream DAC samples from another DDR4. I modified the reference designs and made sure that the HDL workflow advisor detects the changes in the plugin_rd.m. I also manually added 2 AXI4Master in plungin_rd.com. Everything is good till I make the Vivado project and it fails there! The failure is related to connecting the AXI to DDR4 MIG! I did everything you could possibly imagine, but no luck! That would be great if someone could provide instructions which work! Appreciate any response.

RE: How to enable both DDR4s on ZCU208 RFSoC Simulink models where I like to have both ADC and DACs streaming to/from separate DDR4?

Saeedk74 — Wed, 11 Jun 2025 01:21:14 GMT

Hi, thank you very much for the reply. Yes, I have modified the vivado project from other examples and added axi_interconnects and the 2nd MIG for the 2nd DDR4 interface. I also generated .tcl file within vivado. But the issue I have is connecting the Simulink to the modified .tcl files! It always overwrites what I do on .tcl files when I am creating the Vivado project under HDL workflow advisor. That's where I am stuck! I have modified the reference designs and plug-ins and everything works in Workflow advisor except where I get to creating the Vivado project!

RE: How to enable both DDR4s on ZCU208 RFSoC Simulink models where I like to have both ADC and DACs streaming to/from separate DDR4?

lightcollector — Wed, 11 Jun 2025 00:45:26 GMT

Hi, If you haven't already figured out what your issue is, there isn't enough here for me to pinpoint what is going on with respect to your unique system.

If any partial Vivado project is created, take a look at that from within Vivado itself. If there isn't any Vivado project, then I recommend generating one with an example design that is closest to where you want to go. Then take that design and modify it using purely Vivado to add the new functionality. Then export the block design tcl and use it to double check your unique customization of the various .m and .tcl files.

If you have already done the above, then my guess would be that you haven't modified enough of the existing hard coded wiring that MathWorks HDL Coder for RFSoC creates. One approach would be to add after HDL Coder for ZCU208 tcl does its' things, some tcl that deletes portions of the original design and then re-add and/or re-wire the old and new pieces to do what you want. If you could do this in the plugin then you could continue to rely on your Simulink simulation. But you could add your custom DDR purely through Vivado tcl scripts and for Simulink, add the memory external to the DUT; this would allow you to do some amount of simulation within Simulink still.

HDL Coder for RFSoC builds a fairly rigid platform around the users single clock domain DUT algorithm Simulink block. This makes it easy for users to get started with the tradeoff that not all board features are usable or easy to use.

Keep us posted on your progress, thanks

RE: How to enable both DDR4s on ZCU208 RFSoC Simulink models where I like to have both ADC and DACs streaming to/from separate DDR4?

Saeedk74 — Mon, 02 Jun 2025 04:55:11 GMT

I also modified the add_system.tcl as below:

if {[string first "zcu208" $BOARD_PART ]!=-1} {
# Create instance: ddr4_0, and set properties
set ddr4_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_0 ]
set_property -dict [ list \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
CONFIG.C0.CS_WIDTH {2} \
CONFIG.C0.DDR4_AxiAddressWidth {32} \
CONFIG.C0.DDR4_AxiDataWidth {256} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \
CONFIG.C0.DDR4_Clamshell {true} \
CONFIG.C0.DDR4_DataWidth {32} \
CONFIG.C0.DDR4_InputClockPeriod {3334} \
CONFIG.C0.DDR4_MemoryPart {MT40A1G8WE-075E} \
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_c0_300mhz} \
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c0} \
CONFIG.RESET_BOARD_INTERFACE {reset} \
] $ddr4_0

puts "DDR4 block: $ddr4_0"

# Create instance: ddr4_1, and set properties
set ddr4_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ddr4:2.2 ddr4_1 ]
set_property -dict [ list \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
CONFIG.C0.CS_WIDTH {2} \
CONFIG.C0.DDR4_AxiAddressWidth {32} \
CONFIG.C0.DDR4_AxiDataWidth {256} \
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {3} \
CONFIG.C0.DDR4_Clamshell {true} \
CONFIG.C0.DDR4_DataWidth {32} \
CONFIG.C0.DDR4_InputClockPeriod {3334} \
CONFIG.C0.DDR4_MemoryPart {MT40A1G8WE-075E} \
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_sysclk_c1_300mhz} \
CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_c1} \
CONFIG.RESET_BOARD_INTERFACE {reset} \
] $ddr4_1

}

RE: DAC sampling frequency over 7 Gsps with ZCU208

lightcollector — Wed, 09 Oct 2024 15:22:20 GMT

Hi, I did reach out to MathWorks and we re-concluded the original poster's issue was resolved. There was an official trouble ticket created for this issue and the code modifications were officially released for R2023a via the HDL Coder for RFSoC support package. For the ZCU216, the correct support package is nearly seamlessly installed. So this shouldn't be a task of chasing down the correct version of the support package, it's a matter of having MathWorks tools at least of version R2023a and having them install the package with the fixes.

There are some additional conditionals of using above 7gsps (IMR mode) for the DACs. More details can be found in AMD's PG269 document. This link at least worked when I posted it: https://docs.amd.com/r/en-US/pg269-rf-data-converter. See the sections for IMR mode.

If you are abiding by AMD's restrictions and it is still not working for you, please provide some more details of the issues you are seeing.

Kind regards

DAC sampling frequency over 7 Gsps with ZCU208

McG — Thu, 05 May 2022 22:59:54 GMT

Hello everyone,

I'm working with a ZCU208 board by using the matlab/simulink board support provided at this link:

https://rfsoc-hdlcoder.readthedocs.io/en/latest/zcu208.html

All the examples work fine and I'm capable to modify the templates for my purposes without particular problems.

The only issue is related to when I try to set the sampling rate of the DACs over 7 Gsps, namely 8.6 GHz.

I receive the error: Maximum DAC frequency when using FullNyquistDUC is 7000 MHz

Of course, I'm not using Fully Nyquist mode, but I set the IMR filter in High Pass mode as depicted in the screenshot below:

It seems that the problem is connected with soc.RFDataConverter object provided by Xilinx, but I'm not sure.

Did anyone have the same problem or is able to replicate it?

Regards

RE: DAC sampling frequency over 7 Gsps with ZCU208

lightcollector — Thu, 03 Oct 2024 18:55:22 GMT

Hi, No updated news, but I will re-communicate the issue. In the thread above is an email addres to reach out to MathWorks or if you have paid support, please approach them with the issue. MathWorks fully own the ZCU216 support and tools, and most of the affected peices are re-used for the ZCU208 but Avnet doesn't directly control those parts.

Kind regards