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Software Application Development Question about booting both Zynq A9 cores
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Question about booting both Zynq A9 cores

Former Member
Former Member over 12 years ago

Hello, I am a new Zedboard user.  I am trying to create a simple project in which the two Zynq A9 cores boot and run independently.  After reviewing the Zynq TRM and software developeru2019s guide, I have a few questions:

1) Does each A9 core have its own BootROM, or is there a single shared BootROM?

2) If there are separate BootROMs:
- in order to boot both A9 cores, should I create separate BOOT.BIN images, one containing FSBL_0 + PL bitstream + CPU_0 user software, and the other containing FSBL_1 + CPU_1 user software?
- if so, how does one program separate BOOT.BIN images such that each CPU sees the correct version of the BOOT.BIN file?

3) If there is a single BootROM:
- which A9 core runs code after reset is released?  What happens to the other A9 core?
- should my BOOT.bin image include separate partitions for the CPU_0 user software and the CPU_1 user software?
- how does one modify the standard FSBL in order to hand off execution of each CPU to its associated user software?

Thank you very much for any insight that you can provide!

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  • zedhed
    0 zedhed over 12 years ago

    Hi wolf000,

    Xilinx UG585 (also known as the Zynq-7000 Technical Reference Manual) is one of our best friends when it comes to these types of questions.

    I am looking at V1.2 which can be found here:

    http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

    On page 140, there is a section that covers starting code on CPU1.  According to this you would use the single BootROM to boot CPU0.  You would need your Stage 1 boot loader (FSBL) or later stage boot loader or application to perform the indicated tasks.

    I have not seen any examples of this being done but from what I can tell, it is up to CPU0 to bring CPU1 up and running with application code.

    Regards,

    -Kevin

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  • Former Member
    0 Former Member over 12 years ago in reply to zedhed

    Hi Kevin:

    Thank you very much for your reply!  I had somehow missed that section in the TRM -- it definitely answers my question.  Thanks again for your help.

    Jonathan

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  • Former Member
    0 Former Member over 12 years ago

    Hi,

    I'm trying to boot up both processors using a standard FSBL generated with the SDK. I have implemented the TRM instructions to copy the execution address to 0xfffffff0 and then I send a asm("sev") command. The .mcs file is compiled using the SDK 14.3 tools. The second processor does not boot. I think that somehow the second .elf file is not copied into the correct ram start address.
    Any help would be appreciated.
    Thanks
    Wietz

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  • Former Member
    0 Former Member over 12 years ago

    I have managed to get both processors to correctly boot from QSPI. I did this by implementing the below mentioned instructions.
    http://www.xilinx.com/support/answers/51956.htm
    After this I added the init code in the FSBL to copy the boot address to address 0xfffffff0 and to send the SEV command. I'm using ISE 14.3.

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  • Former Member
    0 Former Member over 12 years ago in reply to Former Member

    is it possible to booting both Zynq A9 cores in MMC boot mode and JTAG boot mode?

    Also can please share the init code changes in FSBL?

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  • ejubenville
    0 ejubenville over 11 years ago in reply to Former Member

    In TRM v1.6 (June 28,2013), the section is named "Starting Code on the CPU1", on page 173, within paragraph 6.3.8 "Post BootROM State".

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  • Former Member
    0 Former Member over 11 years ago in reply to Former Member

    I'm trying to replicate what you did and if you could specify what init code you placed in the FSBL and where that would be greatly appreciated.  I'm trying to boot both cores off the SD card, though I'll have to try QSPI and see if I have more luck there.

    I'm running ISE 14.4 and the imagemover.c file seems to be somewhat different from what that link covered.  Nonetheless, I'll give it a go in 14.3.

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