Software Application Development - Recent Threads

Zynq FSBL is unable to Load BOOT.bin from user selected EMMC offset sector (partition)

adielement — Mon, 19 May 2025 09:29:43 GMT

I am working on Zynq-7030 custom board, (software: Vivado 2019.1 → SDK 2019.1).

I have successfully accessed emmc (mmc1 in my case). Created partitions and made understanding of all emmc related commands. My board has two boot modes. One is for SD card and other is QSPI boot.

To load images from EMMC, I need to store bootloader at QSPI (since boot mode is QSPI), so that bootloader boots first and then proceeds to other images loading, that are placed at emmc.

I want to separately load boot.bin, kernel image, dtb and rootfs for each partition of emmc, based on whatever user selects at bootup. In simple words, there should be a user code that asks from user to select the partition to boot from. Say partition 3 is selected, the boot.bin , kernel image, dtb and rootfs corresponding that partition 3 will be booted up and others will not be booted.

I did research on this and found that BootROM allows FSBL to boot from QSPI to OCM. Now I am stuck in customizing FSBL to take user input and then load corresponding images. I made a simple design in Vivado and enabled only EMMC (mmc1/ sd1) and disabled SD (mmc0/sd0) then generated fsbl.elf from SDK. The fsbl.elf is generated by default method, so it does not take user input and then can load corresponding images according to that user input.

I need way out for this. I have beginner level expertise in embedded C so I need help in how to read the offset sector of EMMC to laod BOOT.bin (that was stored using dd command in the EMMC).

Is my understanding of this approach is correct or I need to adapt alternate for this? If it is correct then I will appreciate help in FSBL code customization.

Mysterious syntax error with "set" command in TCL script

quadzilla — Mon, 06 May 2024 13:49:29 GMT

Another Linux vs Windows issue. We have a TCL script that works under Linux when we use "vitis -s <scriptname>", but it gives us problems at the following line under Windows. Any idea what's going wrong here?

Why use Linux instead of Windows?

quadzilla — Fri, 03 May 2024 20:05:25 GMT

I have seen people recommend doing development under Linux rather than Windows. Can anyone give me a list of reasons for or against using Linux for the development environment? I'd like to present a case to my bosses.

Having trouble building MBox application

quadzilla — Tue, 16 Apr 2024 15:20:05 GMT

I am trying to use the sample MBox code in data/embeddedsw/XilinxProcessorIPLib/drivers/mbox_v4_6 but encountered a lot of compilation errors.

I built my block design as shown below, generated an XSA file, and then used that to build my software application. I found that the resultant xparameters.h file wasn't compatible with the sample MBox code though. For example, xmbox_example.c is looking for XPAR_MBOX_4_DEVICE_ID, but my xparameters.h file only has XPAR_MBOX_0_DEVICE_ID and XPAR_MBOX_1_DEVICE_ID. None of the macros in my XMbox_ConfigTable[] can be found in xparameters.h either.

Any tips on what I should be doing?

How to select debug vs release when building application in Vitis Unified IDE?

quadzilla — Thu, 04 Apr 2024 19:56:50 GMT

The subject line says it all. I see the Build command in the Vitis Unified IDE, but I don't see where I would specify if it should compile the debug or the run/release version. How do I do that?

Block design: How to read and write to block RAM?

quadzilla — Wed, 21 Feb 2024 23:26:22 GMT

This is surely a naive question. I saw how one can use a block memory generator in the block designs. It's not clear to me how one can read from or write to the block RAM using the block designs though. At least, I couldn't find any IP to accomplish this task.

Can this be done via block design? Or can it only be done via supplementary HDL code? (I lack experience when it comes to doing so via Verilog or VHDL, so I was hoping that a block design would do the trick.)

Vitis Unified IDE gets stuck when selecting OS and processor

quadzilla — Tue, 20 Feb 2024 15:38:00 GMT

I'm trying to learn how to use the Vitus Unified IDE2023.2, but the online documentation and tutorials seem a bit sparse.

I tried to create a new platform component within an empty workspace. After I select an XSA file though, Vitis gets stuck at the step shown below. The software doesn't hang but it just keeps spinning at this point.

Some postings that I found online suggest that I need to install a device tree generator. Is this so? Our team is using Windows and the instructions that I found were all for Linux, so I don't know what to make of that.

CPU1 watchdog functionality on ZEDBOARD (XC 7Z020)

1_jiten — Fri, 08 Sep 2023 04:13:11 GMT

Hello All,

I want to understand how CPU1 watchdog works like how to enable, disable and set it. I have a zedboard and I have already installed Xilinx software development kit and Xilinx platform studio.

I have successfully run XAP1078 application so i want to add this CPU1 watchdog functionality in that app only or if there is any other separate code that will also works, so can you please share some example code

ZynqMP PS UART 1 Polled Mode Example Issue with Remote Processor

fastian16 — Thu, 07 Sep 2023 11:33:48 GMT

Hi,

I am working to test PS-UART1 in ZynqMP (UltraZed Som). I am running UART polled mode example to test PS-UART 1.

When I run this example application via JTAG from SDK Debugger, it runs successfully. UART Self Test and UART Internal Loopback Passes Successfully.

After that I generate a petalinux build to boot image from SD-Card in Ultrazed-Som. Then I run same application via following commands,

echo UARTSelfTest.elf > /sys/class/remoteproc/remoteproc0/firmware
echo start > /sys/class/remoteproc/remoteproc0/state

-In this case, the PS-UART1 goes to reset state when the following function is called in the application XUartPs_SetBaudRate(InstancePtr, BaudRate).

The code for PS-UART Self Test is attached here.

/******************************************************************************
*
* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file xuartps_polled_example.c
*
* This file contains an example using the XUartPs driver in polled mode.
*
* This function sends data and expects to receive the data thru the device
* using the local loopback mode.
*
* @note
* If the device does not work properly, the example may hang.
*
* MODIFICATION HISTORY:
* <pre>
* Ver Who Date Changes
* ----- ------ -------- -----------------------------------------------
* 1.00a drg/jz 01/13/10 First Release
* 1.03a sg 07/16/12 Modified the device ID to use the first Device Id
* Removed the printf at the start of the main
* </pre>
******************************************************************************/

/***************************** Include Files *********************************/

#include "xparameters.h"
#include "xuartps.h"
#include "xil_printf.h"

/************************** Constant Definitions *****************************/

/*
* The following constants map to the XPAR parameters created in the
* xparameters.h file. They are defined here such that a user can easily
* change all the needed parameters in one place.
*/
#define UART_DEVICE_ID XPAR_XUARTPS_1_DEVICE_ID

/*
* The following constant controls the length of the buffers to be sent
* and received with the device, this constant must be 32 bytes or less since
* only as much as FIFO size data can be sent or received in polled mode.
*/
#define TEST_BUFFER_SIZE 32

/**************************** Type Definitions *******************************/

/***************** Macros (Inline Functions) Definitions *********************/

/************************** Function Prototypes ******************************/

int UartPsPolledExample(u16 DeviceId);

/************************** Variable Definitions *****************************/

XUartPs Uart_PS; /* Instance of the UART Device */

/*
* The following buffers are used in this example to send and receive data
* with the UART.
*/
static u8 SendBuffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */
static u8 RecvBuffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */


/*****************************************************************************/
/**
*
* Main function to call the Uart Polled mode example.
*
* @param None
*
* @return XST_SUCCESS if succesful, otherwise XST_FAILURE
*
* @note None
*
******************************************************************************/
#ifndef TESTAPP_GEN
int main(void)
{
int Status;

usleep(5000);

xil_printf("Hello World\r\n");

Status = UartPsPolledExample(UART_DEVICE_ID);

if (Status != XST_SUCCESS)
{
xil_printf("UART Polled Mode Example Test Failed\r\n");
return XST_FAILURE;
}


u32* uart_pll = 0xff5e0020;

// Release UART from reset state by clearing TXRST and RXRST bits
u32 control_reg_value = *uart_pll;
xil_printf("IO PLL Control Register = %x \r\n",control_reg_value);

xil_printf("Successfully ran UART Polled Mode Example Test\r\n");

return XST_SUCCESS;

}
#endif
/*****************************************************************************/
/**
*
* This function does a minimal test on the XUartPs device in polled mode.
*
* This function sends data and expects to receive the data thru the UART
* using the local loopback mode.
*
*
* @param DeviceId is the unique device id from hardware build.
*
* @return XST_SUCCESS if successful, XST_FAILURE if unsuccessful
*
* @note
* This function polls the UART, it may hang if the hardware is not
* working correctly.
*
****************************************************************************/
int UartPsPolledExample(u16 DeviceId)
{
int Status;
XUartPs_Config *Config;
unsigned int SentCount;
unsigned int ReceivedCount;
u16 Index;
u32 LoopCount = 0;

/*
* Initialize the UART driver so that it's ready to use.
* Look up the configuration in the config table, then initialize it.
*/


// Address of the UART PS control register
u32* uart_cr = (volatile u32*)(XPAR_PSU_UART_1_BASEADDR + XUARTPS_CR_OFFSET);

// Release UART from reset state by clearing TXRST and RXRST bits
u32 control_reg_value = *uart_cr;
xil_printf("UART Control Register Before LookUp = %x \r\n",control_reg_value);



Config = XUartPs_LookupConfig(DeviceId);
if (NULL == Config)
{
xil_printf("UART PS Lookup Config Failed\r\n");
return XST_FAILURE;
}
else
{
xil_printf("UART PS Lookup Config Success\r\n");
}



// Release UART from reset state by clearing TXRST and RXRST bits
control_reg_value = *uart_cr;
xil_printf("UART Control Register After Lookup = %x \r\n",control_reg_value);


Status = XUartPs_CfgInitialize(&Uart_PS, Config, Config->BaseAddress);
if (Status != XST_SUCCESS)
{
xil_printf("UART PS CFG Init Failed\r\n");
return XST_FAILURE;
}
{
xil_printf("UART PS CFG Init Success\r\n");
}


control_reg_value = *uart_cr;
xil_printf("UART Control Register After INIT = %x \r\n",control_reg_value);

/*
xil_printf("UART PS Before Reset\r\n");

XUartPs_ResetHw(XPAR_PSU_UART_1_BASEADDR);

xil_printf("UART PS After Reset\r\n");

usleep(5000);
*/

/* Check hardware build. */
Status = XUartPs_SelfTest(&Uart_PS);
if (Status != XST_SUCCESS)
{
xil_printf("UART PS Self Test Failed\r\n");
return XST_FAILURE;
}
else
{
xil_printf("UART PS Self Test Success\r\n");
}

/* Use local loopback mode. */
XUartPs_SetOperMode(&Uart_PS, XUARTPS_OPER_MODE_LOCAL_LOOP);

/*
* Initialize the send buffer bytes with a pattern and zero out
* the receive buffer.
*/
for (Index = 0; Index < TEST_BUFFER_SIZE; Index++)
{
SendBuffer[Index] = '0' + Index;
RecvBuffer[Index] = 0;
}

/* Block sending the buffer. */
SentCount = XUartPs_Send(&Uart_PS, SendBuffer, TEST_BUFFER_SIZE);
if (SentCount != TEST_BUFFER_SIZE)
{
xil_printf("UART PS Data Sent Failed\r\n");
return XST_FAILURE;
}
else
{
xil_printf("Sent Count = %d\r\n",SentCount);
}

/*
* Wait while the UART is sending the data so that we are guaranteed
* to get the data the 1st time we call receive, otherwise this function
* may enter receive before the data has arrived
*/
while (XUartPs_IsSending(&Uart_PS))
{
LoopCount++;
}

xil_printf("Data Sent Completed\r\n");

/* Block receiving the buffer. */
ReceivedCount = 0;
while (ReceivedCount < TEST_BUFFER_SIZE)
{
ReceivedCount +=
XUartPs_Recv(&Uart_PS, &RecvBuffer[ReceivedCount],
(TEST_BUFFER_SIZE - ReceivedCount));
}

xil_printf("Received Count = %d\r\n",ReceivedCount);
/*
* Check the receive buffer against the send buffer and verify the
* data was correctly received
*/
for (Index = 0; Index < TEST_BUFFER_SIZE; Index++)
{
xil_printf("Send Data = %d\r\n",SendBuffer[Index]);
xil_printf("Received Data = %d\r\n",RecvBuffer[Index]);

if (SendBuffer[Index] != RecvBuffer[Index])
{
return XST_FAILURE;
}
else
{
xil_printf("Data Matched Success\r\n");
}
}

xil_printf("Internal Loopback Tested Successfully\r\n");

/* Restore to normal mode. */
XUartPs_SetOperMode(&Uart_PS, XUARTPS_OPER_MODE_NORMAL);

return XST_SUCCESS;
}

Debugging stuck in asm_vector.S

Jonathan101 — Wed, 08 Mar 2023 14:33:26 GMT

Hi.

I am working with Ultrazed ev SOM in Viits and Vivado 2020.2.

I am trying to instantiate number of Xilinx Ip cores (spi,iic,uart) and use Xilinx drivers code

in Vitis. based on hw design with axi_bram_controller.

When the debug reach line with Xil_In16:

Xil_In16(XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR+MEM_OFF+addr*2);

it goes to asm_vector.S file to

b SErrorInterruptHandler line and stuck in that file.

I am using vitis 2020.2 app on ultrascale+ on Avnet ultrazed ev som. The program crash to asm_vectors.s file after xil_out function.

Can someone from the community hint on the root cause?

Build errors, petalinux 2022.2, u96v2_sbc_base_2022_2.bsp

rgallic — Thu, 02 Mar 2023 15:05:55 GMT

I am seeing many errors when trying to build a petalinux project using u96v2_sbc_base_2022_2.bsp.

First error is:

rsync: link_stat "/opt/pkg/petalinux/2022.2/components/misc/yocto_machines/u96v2-sbc.conf" failed: No such file or directory (2)
rsync error: some files/attrs were not transferred (see previous errors) (code 23) at main.c(1207) [sender=3.1.3]

I can find u96v2-sbc.conf in directory ./project-spec/meta-avnet/conf/machine/u96v2-sbc.conf.

Do I need to copy this to /opt/pkg/petalinux/2022.2/components/misc/yocto_machines/ ?

Next is a warning:

WARNING: /home/developer/u96v2_sbc_base_2022_2/project-spec/meta-avnet/recipes-apps/factest-launcher/factest-launcher.bb: Unable to get checksum for factest-launcher SRC_URI entry factest-launcher.sh: file could not be found

Followed by:

WARNING: cmake-3.21.1-r0 do_package_write_rpm_setscene: Failed to fetch URL file://1c/2a/sstate:cmake:cortexa72-cortexa53-xilinx-linux:3.21.1:r0:cortexa72-cortexa53:7:1c2afefcb6e91e36c93f739dbcefbfbad6c908b3ff78153003ab3651ef81f3d3_package_write_rpm.tgz.siginfo;downloadfilename=1c/2a/sstate:cmake:cortexa72-cortexa53-xilinx-linux:3.21.1:r0:cortexa72-cortexa53:7:1c2afefcb6e91e36c93f739dbcefbfbad6c908b3ff78153003ab3651ef81f3d3_package_write_rpm.tgz.siginfo, attempting MIRRORS if available
ERROR: cmake-3.21.1-r0 do_package_write_rpm_setscene: Fetcher failure: Unable to find file file://1c/2a/sstate:cmake:cortexa72-cortexa53-xilinx-linux:3.21.1:r0:cortexa72-cortexa53:7:1c2afefcb6e91e36c93f739dbcefbfbad6c908b3ff78153003ab3651ef81f3d3_package_write_rpm.tgz.siginfo;downloadfilename=1c/2a/sstate:cmake:cortexa72-cortexa53-xilinx-linux:3.21.1:r0:cortexa72-cortexa53:7:1c2afefcb6e91e36c93f739dbcefbfbad6c908b3ff78153003ab3651ef81f3d3_package_write_rpm.tgz.siginfo anywhere. The paths that were searched were:
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
WARNING: whetstone-1.2-r0 do_populate_lic_setscene: Failed to fetch URL file://9c/a2/sstate:whetstone::1.2:r0::7:9ca2225568727487f5a1ef1ebc4175a179bc0bcc64335ad596ff49d3179a630f_populate_lic.tgz.siginfo;downloadfilename=9c/a2/sstate:whetstone::1.2:r0::7:9ca2225568727487f5a1ef1ebc4175a179bc0bcc64335ad596ff49d3179a630f_populate_lic.tgz.siginfo, attempting MIRRORS if available
ERROR: whetstone-1.2-r0 do_populate_lic_setscene: Fetcher failure: Unable to find file file://9c/a2/sstate:whetstone::1.2:r0::7:9ca2225568727487f5a1ef1ebc4175a179bc0bcc64335ad596ff49d3179a630f_populate_lic.tgz.siginfo;downloadfilename=9c/a2/sstate:whetstone::1.2:r0::7:9ca2225568727487f5a1ef1ebc4175a179bc0bcc64335ad596ff49d3179a630f_populate_lic.tgz.siginfo anywhere. The paths that were searched were:
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
WARNING: cpufrequtils-008-r5 do_package_qa_setscene: Failed to fetch URL file://25/24/sstate:cpufrequtils:cortexa72-cortexa53-xilinx-linux:008:r5:cortexa72-cortexa53:7:252444a1ac5305b43a92253533a8c421b932e84f69611bfe5f1314f836aea409_package_qa.tgz.siginfo;downloadfilename=25/24/sstate:cpufrequtils:cortexa72-cortexa53-xilinx-linux:008:r5:cortexa72-cortexa53:7:252444a1ac5305b43a92253533a8c421b932e84f69611bfe5f1314f836aea409_package_qa.tgz.siginfo, attempting MIRRORS if available
ERROR: cpufrequtils-008-r5 do_package_qa_setscene: Fetcher failure: Unable to find file file://25/24/sstate:cpufrequtils:cortexa72-cortexa53-xilinx-linux:008:r5:cortexa72-cortexa53:7:252444a1ac5305b43a92253533a8c421b932e84f69611bfe5f1314f836aea409_package_qa.tgz.siginfo;downloadfilename=25/24/sstate:cpufrequtils:cortexa72-cortexa53-xilinx-linux:008:r5:cortexa72-cortexa53:7:252444a1ac5305b43a92253533a8c421b932e84f69611bfe5f1314f836aea409_package_qa.tgz.siginfo anywhere. The paths that were searched were:
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
WARNING: cpufrequtils-008-r5 do_package_write_rpm_setscene: Failed to fetch URL file://ff/6c/sstate:cpufrequtils:cortexa72-cortexa53-xilinx-linux:008:r5:cortexa72-cortexa53:7:ff6c93769a8b05714727b28455aa9401c1850fc1d470d863744bf518d7f356ef_package_write_rpm.tgz.siginfo;downloadfilename=ff/6c/sstate:cpufrequtils:cortexa72-cortexa53-xilinx-linux:008:r5:cortexa72-cortexa53:7:ff6c93769a8b05714727b28455aa9401c1850fc1d470d863744bf518d7f356ef_package_write_rpm.tgz.siginfo, attempting MIRRORS if available
ERROR: cpufrequtils-008-r5 do_package_write_rpm_setscene: Fetcher failure: Unable to find file file://ff/6c/sstate:cpufrequtils:cortexa72-cortexa53-xilinx-linux:008:r5:cortexa72-cortexa53:7:ff6c93769a8b05714727b28455aa9401c1850fc1d470d863744bf518d7f356ef_package_write_rpm.tgz.siginfo;downloadfilename=ff/6c/sstate:cpufrequtils:cortexa72-cortexa53-xilinx-linux:008:r5:cortexa72-cortexa53:7:ff6c93769a8b05714727b28455aa9401c1850fc1d470d863744bf518d7f356ef_package_write_rpm.tgz.siginfo anywhere. The paths that were searched were:
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
WARNING: cpufrequtils-008-r5 do_populate_lic_setscene: Failed to fetch URL file://bc/07/sstate:cpufrequtils::008:r5::7:bc0720160359303365bdcff2452660f93d388ecaf517791f630e2b8280a4cfb0_populate_lic.tgz.siginfo;downloadfilename=bc/07/sstate:cpufrequtils::008:r5::7:bc0720160359303365bdcff2452660f93d388ecaf517791f630e2b8280a4cfb0_populate_lic.tgz.siginfo, attempting MIRRORS if available
ERROR: cpufrequtils-008-r5 do_populate_lic_setscene: Fetcher failure: Unable to find file file://bc/07/sstate:cpufrequtils::008:r5::7:bc0720160359303365bdcff2452660f93d388ecaf517791f630e2b8280a4cfb0_populate_lic.tgz.siginfo;downloadfilename=bc/07/sstate:cpufrequtils::008:r5::7:bc0720160359303365bdcff2452660f93d388ecaf517791f630e2b8280a4cfb0_populate_lic.tgz.siginfo anywhere. The paths that were searched were:
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
WARNING: lighttpd-1.4.59-r0 do_packagedata_setscene: Failed to fetch URL file://72/b7/sstate:lighttpd:cortexa72-cortexa53-xilinx-linux:1.4.59:r0:cortexa72-cortexa53:7:72b767ebb5b45d493d2a710804abeae65aac0e41b2cd5f14b610aa4e6817a62d_packagedata.tgz.siginfo;downloadfilename=72/b7/sstate:lighttpd:cortexa72-cortexa53-xilinx-linux:1.4.59:r0:cortexa72-cortexa53:7:72b767ebb5b45d493d2a710804abeae65aac0e41b2cd5f14b610aa4e6817a62d_packagedata.tgz.siginfo, attempting MIRRORS if available
ERROR: lighttpd-1.4.59-r0 do_packagedata_setscene: Fetcher failure: Unable to find file file://72/b7/sstate:lighttpd:cortexa72-cortexa53-xilinx-linux:1.4.59:r0:cortexa72-cortexa53:7:72b767ebb5b45d493d2a710804abeae65aac0e41b2cd5f14b610aa4e6817a62d_packagedata.tgz.siginfo;downloadfilename=72/b7/sstate:lighttpd:cortexa72-cortexa53-xilinx-linux:1.4.59:r0:cortexa72-cortexa53:7:72b767ebb5b45d493d2a710804abeae65aac0e41b2cd5f14b610aa4e6817a62d_packagedata.tgz.siginfo anywhere. The paths that were searched were:
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
WARNING: whetstone-1.2-r0 do_package_write_rpm_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/whetstone/1.2-r0/temp/log.do_package_write_rpm_setscene.27713
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-benchmark/whetstone/whetstone_1.2.bb:do_package_write_rpm_setscene) failed with exit code '1' - real task will be run instead
WARNING: lmsensors-3.6.0-r0 do_package_qa_setscene: No sstate archive obtainable, will run full task instead.
WARNING: lmsensors-3.6.0-r0 do_package_write_rpm_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/lmsensors/3.6.0-r0/temp/log.do_package_write_rpm_setscene.27812
WARNING: lmsensors-3.6.0-r0 do_populate_lic_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/lmsensors/3.6.0-r0/temp/log.do_populate_lic_setscene.27820
WARNING: libnet-1.2-rc3-r0 do_package_qa_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/libnet/1.2-rc3-r0/temp/log.do_package_qa_setscene.27828
WARNING: libnet-1.2-rc3-r0 do_populate_lic_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/libnet/1.2-rc3-r0/temp/log.do_populate_lic_setscene.27847
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/lmsensors/3.6.0-r0/temp/log.do_package_qa_setscene.27800
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-connectivity/libnet/libnet_1.2-rc3.bb:do_package_qa_setscene) failed with exit code '1' - real task will be run instead
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-bsp/lm_sensors/lmsensors_3.6.0.bb:do_populate_lic_setscene) failed with exit code '1' - real task will be run instead
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-connectivity/libnet/libnet_1.2-rc3.bb:do_populate_lic_setscene) failed with exit code '1' - real task will be run instead
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-bsp/lm_sensors/lmsensors_3.6.0.bb:do_package_qa_setscene) failed with exit code '1' - real task will be run instead
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-bsp/lm_sensors/lmsensors_3.6.0.bb:do_package_write_rpm_setscene) failed with exit code '1' - real task will be run instead
WARNING: libnet-1.2-rc3-r0 do_package_write_rpm_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/libnet/1.2-rc3-r0/temp/log.do_package_write_rpm_setscene.27834
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-connectivity/libnet/libnet_1.2-rc3.bb:do_package_write_rpm_setscene) failed with exit code '1' - real task will be run instead
WARNING: ocl-icd-2.3.0-r0 do_populate_lic_setscene: No sstate archive obtainable, will run full task instead.
WARNING: opencl-clhpp-2.0.15+gitAUTOINC+f7237f3799-r0 do_package_qa_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/ocl-icd/2.3.0-r0/temp/log.do_populate_lic_setscene.27905
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/opencl-clhpp/2.0.15+gitAUTOINC+f7237f3799-r0/temp/log.do_package_qa_setscene.27906
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-core/opencl/ocl-icd_2.3.0.bb:do_populate_lic_setscene) failed with exit code '1' - real task will be run instead
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-core/opencl/opencl-clhpp_git.bb:do_package_qa_setscene) failed with exit code '1' - real task will be run instead
WARNING: ocl-icd-2.3.0-r0 do_package_write_rpm_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/ocl-icd/2.3.0-r0/temp/log.do_package_write_rpm_setscene.27904
WARNING: opencl-clhpp-2.0.15+gitAUTOINC+f7237f3799-r0 do_populate_lic_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/opencl-clhpp/2.0.15+gitAUTOINC+f7237f3799-r0/temp/log.do_populate_lic_setscene.27914
WARNING: ocl-icd-2.3.0-r0 do_package_qa_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/ocl-icd/2.3.0-r0/temp/log.do_package_qa_setscene.27897
WARNING: opencl-clhpp-2.0.15+gitAUTOINC+f7237f3799-r0 do_package_write_rpm_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/opencl-clhpp/2.0.15+gitAUTOINC+f7237f3799-r0/temp/log.do_package_write_rpm_setscene.27907
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-core/opencl/ocl-icd_2.3.0.bb:do_package_qa_setscene) failed with exit code '1' - real task will be run instead
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-core/opencl/ocl-icd_2.3.0.bb:do_package_write_rpm_setscene) failed with exit code '1' - real task will be run instead
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-core/opencl/opencl-clhpp_git.bb:do_package_write_rpm_setscene) failed with exit code '1' - real task will be run instead
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-core/opencl/opencl-clhpp_git.bb:do_populate_lic_setscene) failed with exit code '1' - real task will be run instead
WARNING: linux-firmware-1_20211216-r0 do_packagedata_setscene: Failed to fetch URL file://b6/d9/sstate:linux-firmware:all-xilinx-linux:20211216:r0:allarch:7:b6d9ba067b54e4c67964bc57b4d205cc2befc598b5e5b61747025d753b38d229_packagedata.tgz.siginfo;downloadfilename=b6/d9/sstate:linux-firmware:all-xilinx-linux:20211216:r0:allarch:7:b6d9ba067b54e4c67964bc57b4d205cc2befc598b5e5b61747025d753b38d229_packagedata.tgz.siginfo, attempting MIRRORS if available
ERROR: linux-firmware-1_20211216-r0 do_packagedata_setscene: Fetcher failure: Unable to find file file://b6/d9/sstate:linux-firmware:all-xilinx-linux:20211216:r0:allarch:7:b6d9ba067b54e4c67964bc57b4d205cc2befc598b5e5b61747025d753b38d229_packagedata.tgz.siginfo;downloadfilename=b6/d9/sstate:linux-firmware:all-xilinx-linux:20211216:r0:allarch:7:b6d9ba067b54e4c67964bc57b4d205cc2befc598b5e5b61747025d753b38d229_packagedata.tgz.siginfo anywhere. The paths that were searched were:
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
WARNING: linux-firmware-1_20211216-r0 do_packagedata_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/all-xilinx-linux/linux-firmware/1_20211216-r0/temp/log.do_packagedata_setscene.27927
WARNING: iptraf-ng-1.1.4-r0 do_package_write_rpm_setscene: Failed to fetch URL file://13/0c/sstate:iptraf-ng:cortexa72-cortexa53-xilinx-linux:1.1.4:r0:cortexa72-cortexa53:7:130c01f7801c30fde366c2cf30c8e2a3998ffe19458626890269288780062d4e_package_write_rpm.tgz;downloadfilename=13/0c/sstate:iptraf-ng:cortexa72-cortexa53-xilinx-linux:1.1.4:r0:cortexa72-cortexa53:7:130c01f7801c30fde366c2cf30c8e2a3998ffe19458626890269288780062d4e_package_write_rpm.tgz, attempting MIRRORS if available
ERROR: iptraf-ng-1.1.4-r0 do_package_write_rpm_setscene: Fetcher failure: Unable to find file file://13/0c/sstate:iptraf-ng:cortexa72-cortexa53-xilinx-linux:1.1.4:r0:cortexa72-cortexa53:7:130c01f7801c30fde366c2cf30c8e2a3998ffe19458626890269288780062d4e_package_write_rpm.tgz;downloadfilename=13/0c/sstate:iptraf-ng:cortexa72-cortexa53-xilinx-linux:1.1.4:r0:cortexa72-cortexa53:7:130c01f7801c30fde366c2cf30c8e2a3998ffe19458626890269288780062d4e_package_write_rpm.tgz anywhere. The paths that were searched were:
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
WARNING: nodejs-14.17.1-r0 do_package_write_rpm_setscene: Failed to fetch URL file://34/fa/sstate:nodejs:cortexa72-cortexa53-xilinx-linux:14.17.1:r0:cortexa72-cortexa53:7:34fa991c1f59b42174c7b7197c09029f794580d9f00ddbe6abe9e6beb9b1487b_package_write_rpm.tgz;downloadfilename=34/fa/sstate:nodejs:cortexa72-cortexa53-xilinx-linux:14.17.1:r0:cortexa72-cortexa53:7:34fa991c1f59b42174c7b7197c09029f794580d9f00ddbe6abe9e6beb9b1487b_package_write_rpm.tgz, attempting MIRRORS if available
ERROR: nodejs-14.17.1-r0 do_package_write_rpm_setscene: Fetcher failure: Unable to find file file://34/fa/sstate:nodejs:cortexa72-cortexa53-xilinx-linux:14.17.1:r0:cortexa72-cortexa53:7:34fa991c1f59b42174c7b7197c09029f794580d9f00ddbe6abe9e6beb9b1487b_package_write_rpm.tgz;downloadfilename=34/fa/sstate:nodejs:cortexa72-cortexa53-xilinx-linux:14.17.1:r0:cortexa72-cortexa53:7:34fa991c1f59b42174c7b7197c09029f794580d9f00ddbe6abe9e6beb9b1487b_package_write_rpm.tgz anywhere. The paths that were searched were:
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
/home/developer/u96v2_sbc_base_2022_2/build/sstate-cache
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/core/meta/recipes-kernel/linux-firmware/linux-firmware_20211216.bb:do_packagedata_setscene) failed with exit code '1' - real task will be run instead
WARNING: opencl-headers-git-r0 do_populate_lic_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/opencl-headers/git-r0/temp/log.do_populate_lic_setscene.27937
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-core/opencl/opencl-headers_git.bb:do_populate_lic_setscene) failed with exit code '1' - real task will be run instead
WARNING: nodejs-14.17.1-r0 do_package_write_rpm_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/nodejs/14.17.1-r0/temp/log.do_package_write_rpm_setscene.27951
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-devtools/nodejs/nodejs_14.17.1.bb:do_package_write_rpm_setscene) failed with exit code '1' - real task will be run instead
WARNING: iptraf-ng-1.1.4-r0 do_populate_lic_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/iptraf-ng/1.1.4-r0/temp/log.do_populate_lic_setscene.27940
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-devtools/iptraf/iptraf-ng_1.1.4.bb:do_populate_lic_setscene) failed with exit code '1' - real task will be run instead
WARNING: nodejs-14.17.1-r0 do_package_qa_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/nodejs/14.17.1-r0/temp/log.do_package_qa_setscene.27941
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-devtools/nodejs/nodejs_14.17.1.bb:do_package_qa_setscene) failed with exit code '1' - real task will be run instead
WARNING: iptraf-ng-1.1.4-r0 do_package_qa_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/iptraf-ng/1.1.4-r0/temp/log.do_package_qa_setscene.27938
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-devtools/iptraf/iptraf-ng_1.1.4.bb:do_package_qa_setscene) failed with exit code '1' - real task will be run instead
WARNING: opencl-headers-git-r0 do_package_qa_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/opencl-headers/git-r0/temp/log.do_package_qa_setscene.27933
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-core/opencl/opencl-headers_git.bb:do_package_qa_setscene) failed with exit code '1' - real task will be run instead
WARNING: iptraf-ng-1.1.4-r0 do_package_write_rpm_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/iptraf-ng/1.1.4-r0/temp/log.do_package_write_rpm_setscene.27939
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-devtools/iptraf/iptraf-ng_1.1.4.bb:do_package_write_rpm_setscene) failed with exit code '1' - real task will be run instead
WARNING: opencl-headers-git-r0 do_package_write_rpm_setscene: No sstate archive obtainable, will run full task instead.
ERROR: Logfile of failure stored in: /home/developer/u96v2_sbc_base_2022_2/build/tmp/work/cortexa72-cortexa53-xilinx-linux/opencl-headers/git-r0/temp/log.do_package_write_rpm_setscene.27936
WARNING: Setscene task (/home/developer/u96v2_sbc_base_2022_2/components/yocto/layers/meta-openembedded/meta-oe/recipes-core/opencl/opencl-headers_git.bb:do_package_write_rpm_setscene) failed with exit code '1' - real task will be run instead

I stopped the build here.

Has anyone been able to get a clean build on Petalinux 2022.2 using this BSP?

Zedboard printing garbage/junk over UART

crank1 — Thu, 08 Dec 2022 14:25:45 GMT

Hello, I have been working through some basic examples on the Zedboard, i.e. creating a simple PL fabric to switch an LED upon a button press. The board will program fine, and the system will work (i.e. LEDs and buttons work fine), however, whenever it prints something to the terminal, it appears as junk. I have a cable plugged into the J17 (prog) port and the J14 (UART) port. I have tried every baud rate possible, I understand that the standard is 115200, however no baud rate works (have tried on Vitis Terminal, PuTTy and TeraTerm). I have installed the Cypress (now distributed by Infinion) USB to UART drivers and the board comes up on the device manager as a serial device. I have also tried plugging the J14 port into my Macbook and using screen, but it still has the same issue. All the boot jumpers (JP7-JP11) are grounded. I am using Windows 10 and Vivado and Vitis 2022.2. Are there any other reasons as to why it would be printing junk? I have played around with the Linux install on the SD and all works fine when using a serial terminal, so I don't think it is a driver problem. Thanks.

Ultra96-V2 Petalinunx boot error with Vivado custom Design

jpgoncalves — Thu, 06 Oct 2022 14:26:02 GMT

Hello,

How are you?

I am developing a linux application with Petalinux 2020.1 and need to add a custom FPGA design generated from Vivado using the Ultra96-V2 Board preset. The problem is that when i add any peripheral that use interrupts, my linux kernel boot hangs. Howerver, i can boot with a custom bitstream where I only added BLOCK RAM. With this design my kernel boot and a i can write/read from this RAM on FPGA with devmem tool.

This is my linux kernel booting logs when algo using an AXI TIMER IP from Vivado.

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 5.4.0-xilinx-v2020.1 (oe-user@oe-host) (gcc version 9.2.0 (GCC)) #1 SMP Wed Oct 5 12:21:52 UTC 2022
[    0.000000] Machine model: Avnet Ultra96 Rev1
[    0.000000] earlycon: cdns0 at MMIO 0x00000000ff010000 (options '115200n8')
[    0.000000] printk: bootconsole [cdns0] enabled
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created DMA memory pool at 0x000000003ed40000, size 1 MiB
[    0.000000] OF: reserved mem: initialized node rproc@3ed400000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 512 MiB at 0x000000005fc00000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] psci: SMC Calling Convention v1.1
[    0.000000] percpu: Embedded 21 pages/cpu s48664 r8192 d29160 u86016
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: detected: ARM erratum 845719
[    0.000000] Speculative Store Bypass Disable mitigation not required
[    0.000000] Built 1 zonelists, mobility grouping on. Total pages: 515524
[    0.000000] Kernel command line: earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait
[    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[    0.000000] Memory: 1512568K/2094848K available (11836K kernel code, 688K rwdata, 3676K rodata, 704K init, 518K bss, 57992K reserved, 524288K cma-reserved)
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:    RCU event tracing is enabled.
[    0.000000] rcu:    RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] irq-xilinx: /amba/axi-interrupt-ctrl: num_irq=32, sw_irq=0, edge=0x0

I created the petalinux project using Ultra96-V2 2020.1 BSP.

After that, these are the steps i use to add my custom Vivado Design and generate my linux image

petalinux-config --get-hw-description <CUSTOM_HW_DIR_FILES>

petalinux-build -c avenet-image-minimal

petalinux-package --boot --force --u-boot --format BIN --fpga images/linux/system.bit --pmufw images/linux/pmufw.elf --fsbl images/linux/zynqmp_fsbl.elf

After that, i copy BOOT.bin and image.ub too BOOT partition of SD CARD and also copy rootfs.tar.gz to root partition of SD CARD.

u-boot for the avnet ultrazedev board via tftp PHY issue/driver issue(s)u

pe_in_al — Thu, 14 Apr 2022 19:20:19 GMT

I downloaded and built the u-boot-xlnx.git repo, for the avnet ultrazedev board to try to tftp bin files to boot. I am getting the following boot log error messages and need help understanding and resolving the issues.

The issues reported in the boot log are 1)

"ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 9, interface rgmii-id

zynq_gem ethernet@ff0e0000: Failed to read eth PHY id, err: -2

2) "No match for driver 'soc_xilinx_zynqmp'

Some drivers were not found"

I built the u-boot project with the following cmds/procedure:

{

In order to configure Ethernet Phy,

Modify git/u-boot-xlnx/arch/arm/dts/avnet-ultrazedev-som-v1.0.dtsi, line 47.

Change: reg = <0>; to: reg = <9>;

}

export CROSS_COMPILE=/rtems/6/bin/aarch64-rtems6-

export DEVICE_TREE=avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0

make

bootgen -arch zynqmp -image console.bif -0 /media/calvertpt/ZED_BOOT/BOOT.bin -w on

I should mention that this procedure was previously run successfully by colleagues a ffew years ago. I am guessing that the u-boot-xlnx.git project has had many changes in the interim.

The goal is to have uboot boot new kernel/app image files via tftp to avoid wear/ttear on hardware with uSD card operations, and to speed-up development.

Overlapped output at putty while calling a function is written using xuartps.h to send data to uart in normal mode in zynq board 7000 soc?

rai25 — Tue, 22 Mar 2022 03:33:02 GMT

I am trying to send data from zynq soc 7000 board to pc using uart through a function (driver xuartps.h). within the main program, the code works but calling it from function, output at putty gets overlapped. i tried to debug the code but it looks fine and get output as expected. Need help. thanks

code:

#include "platform.h"
#include "xil_printf.h"
#include<stdlib.h>
#include "xuartps.h"


void uart_output(){


        char *p;
        char  tip[100]="\r\n hi : uart_text_multiple time \0";

        u32 transmittedBytes;
        u32  totalTransmittedBytes;
        u32 status;
        u16 byteCnt;


        XUartPs_Config *PiUartConfig;
        XUartPs PiUart;
        byteCnt=0;


        PiUartConfig=XUartPs_LookupConfig(XPAR_PS7_UART_0_DEVICE_ID);

        status = XUartPs_CfgInitialize(&PiUart,PiUartConfig, PiUartConfig->BaseAddress);

        if(status!=XST_SUCCESS)
            print("Uart initialization failed...\n\r");
        status = XUartPs_SetBaudRate(&PiUart, 115200);

        if(status!=XST_SUCCESS)
                print("BaudRATE init failed....\n\r");
        int o=0;

        p =tip;

        while(*p != '\0'){

            byteCnt+=1;
            p++;

            }
        
        p =tip;

        do{
            totalTransmittedBytes=0;


                 while( totalTransmittedBytes<byteCnt+2){
                     transmittedBytes = XUartPs_Send(&PiUart, (u8*)&p[totalTransmittedBytes],byteCnt);
                     totalTransmittedBytes += transmittedBytes;
                 }
                 p++;

        }while(0<10);

}

int main()
{


        init_platform();

        uart_output();
        uart_output();

        cleanup_platform();
    return 0;
}

Looking for FMC_Network_lwIP_2018.2 reference design in UltraZed-EG PCIe Carrier Card.

eerobert — Tue, 22 Feb 2022 16:38:55 GMT

Hi,

In /products/devtools/avnetboardscommunity/w/documents/3544/ultrazed-eg-pcie-carrier-card, there is an item called UltraZed PCIe Carrier Card + FMC Network _lwIP reference designs

However, the link redirects me to SDSoC_Platform_v2018p2rev3p2_1.zip.

Would like know is it the same as the SDSoC_Platform_v2018.2?

And where can I download the FMC_Netowrk_lwIP_2018.2 reference design?

Thanks

2018.3 Petalinux BSP for uz3eg_iocc board

mahadeva.hn — Thu, 18 Mar 2021 07:00:10 GMT

Hi,

We are migrating from ZCU102 to uz3eg_iocc board. All our previous development on petalinux 2018.3 version. When I go through your site i got know that, 2018.3 BSP is not available for uz3eg_iocc board. So please provide me 2018.3 BSP for uz3eg_iocc board.

How to debug linux hard lockup on Xilinx Zynq 7010

pleuba — Wed, 01 Jul 2020 07:05:25 GMT

We have a device using the Zynq 7010, that sometimes produces a hard lockup. The PS runs a linux distro built with buildroot-2018.02.7 and the PL runs some proprietary IPs, communication between both is done through registers and interrupts. We have setup debugging via JTAG, using gdb, openocd and a USB Digilent HS3, this allow us to break into the linux at any time, but when the lockup happens, the debugger is not able to halt the processor (setting the halt bit in the DSCR register did not halt the processor).

What can prevent the processor to be halted ? How can we debug this issue ?

AXI Memory map read access...Zedboard

nightpoison — Thu, 16 Apr 2020 14:36:57 GMT

Hello, I'm working with a co-worker to setup a simple application that handles some data collected from an ADC. He is handling the acquisition of the data from ADC. I'm managing the main application. I've configured a petalinux build which I have up and running on the Zedboad. What I'm looking for is some direction, resources, or examples of accessing the memory space he is storing the data in. He has already set up the memory space. The data will be mapped into 0x400000000 - 0x400003FF - Data[32:0]. I will need to control GPIO for status and system control. Just two: GPIO_1 bit_0 - TRIGGER R/W, and GPIO_1 Bit_1 - DONE RO

I've never used the zedboard or accessed memory directly before. What I'm doing with the data after I retrieve it, I'm good to go. But actually retrieving the data from the memory is where I'm lost. I know I'll be using AXI and I've done some research on how it operates. However, I haven't found any examples of how to actually implement it.

Does someone know of an example or guide I can reference to help development.

Thank you for your time and help.

Best regards,

Michael

driver for display kits

jothin — Tue, 03 Mar 2020 13:30:49 GMT

Hi,

Is updated device driver for 7" LCD or 10" LCD zed_disp_kit available?

Jothi

Help to download zedboard version of xapp1026

filabrasil — Sun, 22 Dec 2019 12:41:11 GMT

I just created an account on zedboard.org but for some reason, the link below doesn't work for me. The other files do but this one don't.

http://zedboard.org/sites/default/files/design/xapp1026_zedboard.zip

Can anybody send a mirror link.

Thanks

UltraZed-EV (zynqmp) not generating interrupts for GPIOs

jlindquist74 — Thu, 07 Nov 2019 20:11:53 GMT

I'm testing software I'm writing for a custom target, using the UltraZedEV on the Avnet carrier card. Particularly, I'm using the SW5 DIP switches to stand in for switches on the target which should trigger interrupts on the rising transition. However, no interrupts are ever generated. I have the GPIO pins exported in sysfs as gpio504-511, the edge set to "rising", and open file descriptors on their "value" nodes, watched by poll() for POLLPRI. But poll() never returns events on those fd's revents fields. Further, /proc/interrupts shows no interrupts have been generated for them:

root@avnetuz:~# cat /proc/interrupts

CPU0 CPU1 CPU2 CPU3

3: 10390 311753 2886 73304 GICv2 30 Level arch_timer

6: 0 0 0 0 GICv2 67 Level ff9905c0.mailbox

7: 0 0 0 0 GICv2 175 Level arm-pmu

8: 0 0 0 0 GICv2 176 Level arm-pmu

9: 0 0 0 0 GICv2 177 Level arm-pmu

10: 0 0 0 0 GICv2 178 Level arm-pmu

12: 0 0 0 0 GICv2 156 Level zynqmp-dma

13: 0 0 0 0 GICv2 157 Level zynqmp-dma

14: 0 0 0 0 GICv2 158 Level zynqmp-dma

15: 0 0 0 0 GICv2 159 Level zynqmp-dma

16: 0 0 0 0 GICv2 160 Level zynqmp-dma

17: 0 0 0 0 GICv2 161 Level zynqmp-dma

18: 0 0 0 0 GICv2 162 Level zynqmp-dma

19: 0 0 0 0 GICv2 163 Level zynqmp-dma

21: 0 0 0 0 GICv2 109 Level zynqmp-dma

22: 0 0 0 0 GICv2 110 Level zynqmp-dma

23: 0 0 0 0 GICv2 111 Level zynqmp-dma

24: 0 0 0 0 GICv2 112 Level zynqmp-dma

25: 0 0 0 0 GICv2 113 Level zynqmp-dma

26: 0 0 0 0 GICv2 114 Level zynqmp-dma

27: 0 0 0 0 GICv2 115 Level zynqmp-dma

28: 0 0 0 0 GICv2 116 Level zynqmp-dma

30: 0 0 0 0 GICv2 95 Level eth0, eth0

32: 49 0 0 0 GICv2 50 Level cdns-i2c

33: 0 0 0 0 GICv2 42 Level ff960000.memory-controller

34: 0 0 0 0 GICv2 57 Level axi-pmon

35: 0 0 0 0 GICv2 150 Level nwl_pcie:misc

40: 23 0 0 0 GICv2 47 Level ff0f0000.spi

41: 0 0 0 0 GICv2 58 Level ffa60000.rtc

42: 0 0 0 0 GICv2 59 Level ffa60000.rtc

43: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci]

44: 441 0 0 0 GICv2 80 Level mmc0

45: 2054 0 0 0 GICv2 81 Level mmc1

46: 7348 0 0 0 GICv2 53 Level xuartps

48: 0 0 0 0 GICv2 145 Edge fd4d0000.watchdog

49: 0 0 0 0 GICv2 88 Level ams-irq

50: 0 0 0 0 GICv2 154 Level fd4c0000.dma

51: 64 0 0 0 GICv2 151 Level fd4a0000.zynqmp-display

52: 0 0 0 0 xgpio 0 Edge gpiolib

53: 0 0 0 0 xgpio 1 Edge gpiolib

54: 0 0 0 0 xgpio 2 Edge gpiolib

55: 0 0 0 0 xgpio 3 Edge gpiolib

56: 0 0 0 0 xgpio 4 Edge gpiolib

57: 0 0 0 0 xgpio 5 Edge gpiolib

58: 0 0 0 0 xgpio 6 Edge gpiolib

59: 0 0 0 0 xgpio 7 Edge gpiolib

IPI0: 2421 2110 1330 2071 Rescheduling interrupts

IPI1: 8 6 11 5 Function call interrupts

IPI2: 0 0

Interrupts 52-59 are my GPIOs, but flipping the switches back and forth does nothing.

Is there something I'm missing from my device tree (attached) or something else I need to do to make these interrupts active?

Attachments:

community.element14.com/.../system.dts.txt.zip

PicoZed - Bootable images not booting from SD Card

ashfaque.roomy — Tue, 22 Oct 2019 04:27:56 GMT

Hello everyone,

I am new to the xilinx environment. I have a couple of questions on booting Picozed from SD card.

Note:

I have already gone thru the link(s):

http://zedboard.org/content/how-copy-bootbin-and-imageub-over-sd-card

http://zedboard.org/content/sd-card-advice-zynq-7000-soc-products-0

Here's my configuration:

PICOZED 7015/7030, on PicoZed FMC Carrier Card

Ref:

http://zedboard.org/sites/default/files/documentations/5279-UG-PicoZed-7015-7030-V2_0.pdf

http://zedboard.org/sites/default/files/documentations/PicoZed_FMC_CC_GettingStarted_v2_1-1.pdf

I have followed the Picozed Tutorials, and I can boot Picozed and see the serial console display the values when I boot from Flash (probably termed as QSPI mode?).

Ref:

http://picozed.org/support/documentation/13076

SD-card has the following partitions created:

$ sudo fdisk -l /dev/mmcblk0

Disk /dev/mmcblk0: 14.4 GiB, 15489564672 bytes, 30253056 sectors

Units: sectors of 1 * 512 = 512 bytes

Sector size (logical/physical): 512 bytes / 512 bytes

I/O size (minimum/optimal): 512 bytes / 512 bytes

Disklabel type: dos

Disk identifier: 0x7d78c1c9

Device Boot Start End Sectors Size Id Type

/dev/mmcblk0p1 * 2048 2050047 2048000 1000M b W95 FAT32

/dev/mmcblk0p2 2050048 30253055 28203008 13.5G 83 Linux

I have copied bootable factory images (BOOT.INI and image.ub) to the FAT partition of SD card.

Ref:

PicoZed FMC Carrier Card V2 | Zedboard (Section: PetaLinux SD Card Boot Binaries, z7030 PetaLinux binaries to boot PetaLinux out-of-box image from SD Card)

Q1 - I do not see serial output getting displayed when I try to boot from SD card, and I cannot validate a successful SD card boot. What am I missing something (additional files/etc)?

Ref:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841655/Prepare+Boot+Medium

I built a bootable image for zedboard config, from the following link: https://github.com/buildroot/buildroot/tree/master/board/zynq

Q2 - Would the bootable image built from the link mentioned above work on Picozed 7030?

Q3. How are these bootable images different:

a. Factory built image taken from PicoZed FMC Carrier Card V2 | Zedboard

b. Bootable image built from https://github.com/buildroot/buildroot/tree/master/board/zynq

c. Image built using Xilinx SDK for Picozed (Tutorials under: PicoZed FMC Carrier Card V2 | Zedboard )

Thanks,

Ashfaque

which bsp to use for PicoZed FMC Carrier Card v1

openhacker — Tue, 24 Sep 2019 23:36:44 GMT

I want to build petalinux on FMC Carrier Card v1.

I've already built bare metal applications successfully (I used board definitions for Vivado 2016.04, and then imported them into 2018.3

The board defintions I see on:

PicoZed FMC Carrier Card v1

look like they're for FMC2 (I assume that means V2?)

There's older bsp's which don't even list FMC1 (I assume at FMC1 there was no "versioning"?)

So, since I've never done this before (can I construct a bsp from a baremetal application which runs in the SDK?), where do I get a "good"

bsp from?

Marty

baremetal programming on picozed 7015/7030 (v1)

openhacker — Fri, 16 Aug 2019 02:51:29 GMT

I'm following the tutorial in

Tutorial 2 -- First application - Hello world for Vivado 2016.4 (I got vivado 2016.4 so I can follow the tutorial verbatim)

It says:

8. Click Browse and select the System_wrapper.hdf file generated during the

Export process from Vivado. This will be included in the archive provided by the

hardware engineer. Or, if you are continuing from the first tutorial, you will find

it in a similar location as here:

C:\Avnet\MicroZed\Projects\MZ_Basic_System\MZ_Basic_System.sdk\

I didn't see (or know where to get) the "System_wrapper.hdf file.

So I got 2016.04 vivado.

I followed:

Tutorial 01 Build the Zynq Hardware Platform

for 2016.4

(since that's the newest one -- when I get something working, I'll move on to something newer)

On page 3, it lists a whole range of picozed boards from em.avnet.com. I figured the process would be straightforward.

But attached is what I see (no picozed).

FWIW, I've been doing embedded work for 30 years ;-) This is new for me (I have a client who wants me to do software work,

not hardware work).

I'm interested in getting my jtag adapter working -- but it seems I need a good "board description" to do anything.

marty

Attachments: