element14 Community
element14 Community
    Register Log In
  • Site
  • Search
  • Log In Register
  • Members
    Members
    • Benefits of Membership
    • Achievement Levels
    • Members Area
    • Personal Blogs
    • Feedback and Support
    • What's New on element14
  • Learn
    Learn
    • Learning Center
    • eBooks
    • STEM Academy
    • Webinars, Training and Events
    • More
  • Technologies
    Technologies
    • 3D Printing
    • FPGA
    • Industrial Automation
    • Internet of Things
    • Power & Energy
    • Sensors
    • More
  • Challenges & Projects
    Challenges & Projects
    • Design Challenges
    • element14 presents
    • Project14
    • Arduino Projects
    • Raspberry Pi Projects
    • More
  • Products
    Products
    • Arduino
    • Dev Tools
    • Manufacturers
    • Raspberry Pi
    • RoadTests & Reviews
    • Avnet Boards Community
    • More
  • Store
    Store
    • Visit Your Store
    • Choose Another Store
      • Europe
      •  Austria (German)
      •  Belgium (Dutch, French)
      •  Bulgaria (Bulgarian)
      •  Czech Republic (Czech)
      •  Denmark (Danish)
      •  Estonia (Estonian)
      •  Finland (Finnish)
      •  France (French)
      •  Germany (German)
      •  Hungary (Hungarian)
      •  Ireland
      •  Israel
      •  Italy (Italian)
      •  Latvia (Latvian)
      •  
      •  Lithuania (Lithuanian)
      •  Netherlands (Dutch)
      •  Norway (Norwegian)
      •  Poland (Polish)
      •  Portugal (Portuguese)
      •  Romania (Romanian)
      •  Russia (Russian)
      •  Slovakia (Slovak)
      •  Slovenia (Slovenian)
      •  Spain (Spanish)
      •  Sweden (Swedish)
      •  Switzerland(German, French)
      •  Turkey (Turkish)
      •  United Kingdom
      • Asia Pacific
      •  Australia
      •  China
      •  Hong Kong
      •  India
      •  Korea (Korean)
      •  Malaysia
      •  New Zealand
      •  Philippines
      •  Singapore
      •  Taiwan
      •  Thailand (Thai)
      • Americas
      •  Brazil (Portuguese)
      •  Canada
      •  Mexico (Spanish)
      •  United States
      Can't find the country/region you're looking for? Visit our export site or find a local distributor.
  • Translate
  • Profile
Avnet Boards Forums
  • Products
  • Dev Tools
  • Avnet Boards Community
  • Avnet Boards Forums
  • More
  • Cancel
Avnet Boards Forums
Ultra96 Hardware Design Script make_u96v2_sbc_base.sh of version 2020.2 outputs error
  • Forums
  • Documents
  • Members
  • Mentions
  • Sub-Groups
  • Tags
  • More
  • Cancel
  • New
Avnet Boards Forums requires membership for participation - click to join
Actions
  • Share
  • More
  • Cancel
Forum Thread Details
  • State Suggested Answer
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 44 subscribers
  • Views 428 views
  • Users 0 members are here
  • ultra96
  • 2020.2
  • vivado 2020.2
Related

Script make_u96v2_sbc_base.sh of version 2020.2 outputs error

ece7498
ece7498 7 months ago

Hello,

I am trying to run the 2020.2 make command based on https://github.com/Avnet/petalinux/blob/2020.2/scripts/make_u96v2_sbc_base.sh  .
I have included bdf in Vivado by copy pasting them. I have checkout hdl and petalinux projects to version 2020.2 .

 

I am facing the following error:

When I open the vivado project, I see I am missing an IP:

 

Could you please elaborate on this error? Is anything my fault?

Thanks much,

AE

  • Reply
  • Cancel
  • Cancel
  • narrucmot
    0 narrucmot 7 months ago

    Hi Alexander,

     

    I am unable to duplicate the failure you describe.  Can you share the <>/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.runs/impl_1/runme.log file?

     

    The system_management_wiz is a free IP from Xilinx that is included in the Vivado installation.  I suspect that although Vivado indicates the failure is with this IP, I suspect the real problem is somewhere else.  Are you running a supported Ubuntu OS?  Do you have enough RAM installed, and enough disk space?  Xilinx UG973 can help answer these questions:

    https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug973-vivado-release-notes-install-license.pdf

     

    If your Vivado build has been successful it would have looked more like this:

     

    --Tom

    • Cancel
    • Up 0 Down
    • Reply
    • Verify Answer
    • Reject Answer
    • Cancel
  • ece7498
    0 ece7498 7 months ago in reply to narrucmot

    Hello Tom,

    Thanks for your time. There is no such a file as the synthesis is not completed to run implementation. The error is in this subprocess (../avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.runs/u96v2_sbc_base_system_management_wiz_0_0_synth_1) of synthesis :

     

    *** Running vivado

        with args -log u96v2_sbc_base_system_management_wiz_0_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source u96v2_sbc_base_system_management_wiz_0_0.tcl

     

     

    ****** Vivado v2020.2 (64-bit)

      **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020

      **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020

        ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

     

    source u96v2_sbc_base_system_management_wiz_0_0.tcl -notrace

    INFO: [IP_Flow 19-234] Refreshing IP repositories

    INFO: [IP_Flow 19-1700] Loaded user IP repository '/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/ip'.

    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2020.2/data/ip'.

    Command: synth_design -top u96v2_sbc_base_system_management_wiz_0_0 -part xczu3eg-sbva484-1-i -mode out_of_context

    Starting synth_design

    Attempting to get a license for feature 'Synthesis' and/or device 'xczu3eg'

    INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xczu3eg'

    INFO: [Device 21-403] Loading part xczu3eg-sbva484-1-i

    INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.

    INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes

    INFO: [Synth 8-7075] Helper process launched with PID 13953

    ---------------------------------------------------------------------------------

    Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2519.070 ; gain = 30.902 ; free physical = 38828 ; free virtual = 47125

    ---------------------------------------------------------------------------------

    INFO: [Synth 8-638] synthesizing module 'u96v2_sbc_base_system_management_wiz_0_0' [/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.gen/sources_1/bd/u96v2_sbc_base/ip/u96v2_sbc_base_system_management_wiz_0_0/u96v2_sbc_base_system_management_wiz_0_0.vhd:93]

        Parameter C_INSTANCE bound to: u96v2_sbc_base_system_management_wiz_0_0_axi_xadc - type: string

        Parameter C_FAMILY bound to: kintexu - type: string

        Parameter C_S_AXI_ADDR_WIDTH bound to: 13 - type: integer

        Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer

        Parameter C_INCLUDE_INTR bound to: 1 - type: integer

        Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string

    INFO: [Synth 8-3491] module 'u96v2_sbc_base_system_management_wiz_0_0_axi_xadc' declared at '/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.gen/sources_1/bd/u96v2_sbc_base/ip/u96v2_sbc_base_system_management_wiz_0_0/u96v2_sbc_base_system_management_wiz_0_0_axi_xadc.vhd:142' bound to instance 'U0' of component 'u96v2_sbc_base_system_management_wiz_0_0_axi_xadc' [/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.gen/sources_1/bd/u96v2_sbc_base/ip/u96v2_sbc_base_system_management_wiz_0_0/u96v2_sbc_base_system_management_wiz_0_0.vhd:166]

    INFO: [Synth 8-638] synthesizing module 'u96v2_sbc_base_system_management_wiz_0_0_axi_xadc' [/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.gen/sources_1/bd/u96v2_sbc_base/ip/u96v2_sbc_base_system_management_wiz_0_0/u96v2_sbc_base_system_management_wiz_0_0_axi_xadc.vhd:236]

        Parameter C_INSTANCE bound to: u96v2_sbc_base_system_management_wiz_0_0_axi_xadc - type: string

        Parameter C_FAMILY bound to: kintexu - type: string

        Parameter C_S_AXI_ADDR_WIDTH bound to: 13 - type: integer

        Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer

        Parameter C_INCLUDE_INTR bound to: 1 - type: integer

        Parameter C_SIM_MONITOR_FILE bound to: design.txt - type: string

    INFO: [Synth 8-638] synthesizing module 'u96v2_sbc_base_system_management_wiz_0_0_axi_lite_ipif' [/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.gen/sources_1/bd/u96v2_sbc_base/ip/u96v2_sbc_base_system_management_wiz_0_0/axi_lite_ipif_v1_31_a/hdl/src/vhdl/u96v2_sbc_base_system_management_wiz_0_0_axi_lite_ipif.vhd:241]

        Parameter C_S_AXI_DATA_WIDTH bound to: 32 - type: integer

        Parameter C_S_AXI_ADDR_WIDTH bound to: 13 - type: integer

        Parameter C_S_AXI_MIN_SIZE bound to: 32'b00000000000000000000011111111111

        Parameter C_USE_WSTRB bound to: 1 - type: integer

        Parameter C_DPHASE_TIMEOUT bound to: 64 - type: integer

        Parameter C_ARD_ADDR_RANGE_ARRAY bound to: 384'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000111111100000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000001111111111111

        Parameter C_ARD_NUM_CE_ARRAY bound to: 96'b000000000000000000000000000010000000000000000000000000000001000000000000000000000000000000000001

        Parameter C_FAMILY bound to: kintexu - type: string

    ERROR: [Synth 8-5826] no such design unit 'u96v2_sbc_base_system_management_wiz_0_0_slave_attachment' in library 'work' [/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.gen/sources_1/bd/u96v2_sbc_base/ip/u96v2_sbc_base_system_management_wiz_0_0/axi_lite_ipif_v1_31_a/hdl/src/vhdl/u96v2_sbc_base_system_management_wiz_0_0_axi_lite_ipif.vhd:252]

    ERROR: [Synth 8-285] failed synthesizing module 'u96v2_sbc_base_system_management_wiz_0_0_axi_lite_ipif' [/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.gen/sources_1/bd/u96v2_sbc_base/ip/u96v2_sbc_base_system_management_wiz_0_0/axi_lite_ipif_v1_31_a/hdl/src/vhdl/u96v2_sbc_base_system_management_wiz_0_0_axi_lite_ipif.vhd:241]

    ERROR: [Synth 8-285] failed synthesizing module 'u96v2_sbc_base_system_management_wiz_0_0_axi_xadc' [/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.gen/sources_1/bd/u96v2_sbc_base/ip/u96v2_sbc_base_system_management_wiz_0_0/u96v2_sbc_base_system_management_wiz_0_0_axi_xadc.vhd:236]

    ERROR: [Synth 8-285] failed synthesizing module 'u96v2_sbc_base_system_management_wiz_0_0' [/home/barracuda/Desktop/research/git/0_ultra96/avnet/hdl/projects/u96v2_sbc_base_2020_2/u96v2_sbc_base.gen/sources_1/bd/u96v2_sbc_base/ip/u96v2_sbc_base_system_management_wiz_0_0/u96v2_sbc_base_system_management_wiz_0_0.vhd:93]

    ---------------------------------------------------------------------------------

    Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 2568.977 ; gain = 80.809 ; free physical = 39614 ; free virtual = 47906

    ---------------------------------------------------------------------------------

    RTL Elaboration failed

    INFO: [Common 17-83] Releasing license: Synthesis

    13 Infos, 0 Warnings, 0 Critical Warnings and 5 Errors encountered.

    synth_design failed

    ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details

    INFO: [Common 17-206] Exiting Vivado at Mon Nov  1 16:50:08 2021...

     


    Thanks,
    AE

    • Cancel
    • Up 0 Down
    • Reply
    • Verify Answer
    • Cancel
  • narrucmot
    0 narrucmot 7 months ago in reply to ece7498

    Do you always build Vivado projects under your user "Desktop" folder?  That is an unusual place to clone the Avnet git repositories and build the Vivado project.  More typical would be to clone the repos under /home/barracuda/git/...

     

    Are you running a supported version of Ubuntu?  Can you run the 'lsb_release -a' command and report the result here?

     

    Can you run the 'df' command to report how much disk space you have.  For example, assuming your system disk is /dev/sda1, the command to run to report disk use is 'df -hlT |head -n 1; df -hT |grep sda'

     

    Also, can you open the project in the Vivado GUI and run the following TCL command:
    report_compile_order -used_in synthesis -of [get_ips u96v2_sbc_base_system_management_wiz_0_0]

     

    This is described in a Xilinx forum post I found that I found regarding this particular "ERROR: [Synth 8-5826] no such design unit" error.

    https://support.xilinx.com/s/question/0D52E00006hpiPr/synth-85826-no-such-design-unit-cdcsync-in-library-libcdcv102-erro…

     

    --Tom

    • Cancel
    • Up 0 Down
    • Reply
    • Verify Answer
    • Reject Answer
    • Cancel
  • ece7498
    0 ece7498 7 months ago in reply to narrucmot

    Yes all my project are there.

     

    My Ubuntu version is compatible yes, here is the output:

    barracuda@barracuda:~$ lsb_release -a

    No LSB modules are available.

    Distributor ID: Ubuntu

    Description: Ubuntu 18.04.6 LTS

    Release: 18.04

    Codename: bionic

     

    About the disk space (I have at least 70gb available) :

     

    barracuda@barracuda:~$ df /dev/sda2

    Filesystem     1K-blocks      Used Available Use% Mounted on

    /dev/sda2      490691512 413901380  51794652  89% /

     

    And the tcl-output:

     

     

    Thanks Tom,
    AE

    • Cancel
    • Up 0 Down
    • Reply
    • Verify Answer
    • Cancel
  • narrucmot
    0 narrucmot 7 months ago in reply to ece7498

    You system reports Ubuntu version 18.04.6 LTS, but this is not a supported Ubuntu version for Vivado 2020.2.  From the 2020.2 version of Xilinx UG973:

     

    I have seen strange errors like this occur in situations like this where the minor version of what is installed (v18.04.6 LTS) does not match what is officially supported (v18.04.4 LTS).

     

    I notice your results of the 'report_compile_order' TCL command do not match mine.  My results have an extra compiled file "u96v2_sbc_base_system_management_wiz_0_0_slave_attachment.vhd":

     

    This is the file that lead to the synthesis error your received:

    ERROR: [Synth 8-5826] no such design unit 'u96v2_sbc_base_system_management_wiz_0_0_slave_attachment' in library 'work'

     

    Something is preventing Vivado from generating and synthesizing this file.  I don't know what or why.  Is it possible to revert your Ubuntu version back to v18.04.4 LTS?  I believe that may solve this issue.

     

    --Tom

    • Cancel
    • Up 0 Down
    • Reply
    • Verify Answer
    • Reject Answer
    • Cancel
Element14

element14 is the first online community specifically for engineers. Connect with your peers and get expert answers to your questions.

  • Members
  • Learn
  • Technologies
  • Challenges & Projects
  • Products
  • Store
  • About Us
  • Feedback & Support
  • FAQs
  • Terms of Use
  • Privacy Policy
  • Legal and Copyright Notices
  • Sitemap
  • Cookies

An Avnet Company © 2022 Premier Farnell Limited. All Rights Reserved.

Premier Farnell Ltd, registered in England and Wales (no 00876412), registered office: Farnell House, Forge Lane, Leeds LS12 2NE.

ICP 备案号 10220084.

Follow element14

  • Facebook
  • Twitter
  • linkedin
  • YouTube