• High Temperature normal ?

    Hi, i have a small application with one a53

    running, luts 17%


     

    but the device was very hot. I have measured 60 *C . This is now within the spec but i would know if this is normal.

     

    i am thinking to add a fan to the passive heatsink.



    Greetings Joachim

  • Avnet Ultra96 V-2 booting problem

    I was normally booting my Avnet Ultra96 V-2 from SD-card but today surprisingly no more.

    Current behaviour:

    - I am booting from the same SD card  and the switch is correctly configured

    - No output on the serial Interface

    - The Led D5 INIT(red) is always i…

  • ssd_inception_v2 model and tensorflow on Ultra96v2 (petalinux 2020.2, Vitis AI-1.3)

    Hello,

       I am facing the following problems:

     

    1. When I try to run the tfssd application provided in V1.3 sample for Ultra96V2 board by the below link

    "https://www.hackster.io/AlbertaBeef/vitis-ai-1-3-flow-for-avnet-vitis-platforms-cd0c51 ", i dont get…

  • ON Semiconductor Dual Camera Mezzanine Support

    Hi,

     

    Does anyone know where I can find driver information for the ON Semi Mezzanine board?

     

    So far, I have followed the "Getting Started" document, running the Petalinux image and starting a preinstalled program that shows the camera feed on a monitor. I…

  • Avnet's BSP script and system.bit file

    Hello again!

     

    I am digging to the Avnet's build script and trying to understand it so I can modify and add layers on top of it (meta-ros for example, I will give more information when succeed).


    I am trying to get information about system.bit file, where…

  • [ULTRA96 V2] WiFi and OpenAMP Matrix Multiplication problems.

    Hi All,

     

    I recently got the u96V2-G dev kit and I am tinkering around with it.

    I flashed the delkin SDHC received with ultra96v2_oob_2020_1_201123_8GB.img available on avnet website.

    I am attaching the serial COM putty logs for reference.

    Till now I have…

  • Critical Errors and Warnings when creating BSP for ULTRA96v2 for Vitis 2020.1 Petalinux 2020.1

    Dear All,

     

    I cloned the 2020.1 branch for Avner hdf and petalinux and the master branch for bdf

     

    I run

    source /tools/Xilinx/Vivado/2020.1/settings64.sh

    ~/Avnet/petalinux/scripts$ ./make_ultra96v2.sh

     

     

    Verifying repositories ...

    Checking Environment (Xilinx tools…

  • Trace lengths in Ultra96-V2

    Hello all,

    There is a text document available which lists all trace lengths for Ultra96-V2 board. Is it documented anywhere whether the listed lengths include the corresponding package delays inside the Zynq chip? We are particularly concerned about the…

  • Ultra96-v2 pin function assignment

    Hello All,

     

    I'd like to as you if is it possible to change function assigned to pin (in Vivado I/O planning) related with MIO.

    E.g. change assignment of user LEDs from MIO to EMIO.

    Or do I understand something wrong and MIO connections are fixed and…

  • PS LPDDR4 settings?

    We are trying to understand this option.  My customer is using the exact same part number for LPDDR4 that is used on the Ultra96v2 board.  For LPDDR4, the option for "address mirroring" is disabled.  You can see the check box if you select DDR4…

  • Ultra96 PCB Files

    Does anyone have Gerber files for the Ultra96 PCB?

  • Vivado chipscope and  its configured JTAG frequency/probe specification

    I’m using the Ultra96V2 card with the little JTAG board from Avnet.  Is there a magic frequency for configuring the JTAG frequency with Vivado to get the chipscope/internal logic analyzer(ILA) to work?   I’m using Vivado  2019.2 and just using a clock generated…

  • Power supply alternatives for Ultra96 board?

    Hi,

     

    I missed getting the Power Supply adapter for Ultra96-V2 board.


    What are my alternative ways to power up the board?

    Thank you,

    Debraj

  • using the FPGA on the Ultra96-V2

    Hi,

      I’ve been successful doing hello world, playing with sensors and using PYNQ and now I’m trying to do a simple LED blinky using ONLY the FPGA part of the ULTRA-96-V2 using Verilog. I want drive an LED(s)  totally off board since that is closer to the…

  • Bluetooth issue on Ultra96 V2 board (hci0 command 0x1001 tx timeout)

    Hi

     

    I am trying to bring up the bluetooth on the ultra96 V2 board.

     

    We have tried oob image (http://avnet.me/ultra96-v2-oob) and PYNQ (http://avnet.me/ultra96v2-pynq-image-v2.5) images, and here is the findings:

     

     

    When it is not working we see this UART time…

  • Ultra96-V2 Vivado 2019.2 IOPLL error wrong divider

    Hi there,

     

    I'm new to Xilinx and Ultra96-v2 boards.

    I've been trying to create hardware descripion in Vivado and went to error situation.

    There is wrong IOPLL divider set.

    When I change it to 91 (including enable of divider 2) then I have following…

  • Ultra96v2 How to configure UART driver in python on Jupyter notebook?

    Hello, I am quite new to FPGA and Ultra96v2 board.

     

    what I try to implement is following:

     

    1.  UART communication between Ultra96 v2 board and ST- microcontroller  using on-board expansion pins (J1)

     

    2. Process data comming from the ST-microcontroller on the…

  • 2019.2 BSP Contains Locked IP for PWM_w_Int

    I'm trying to use the 2019.2 Ultra96v2 BSP design as a base to modify and generate a known working petalinux build.  When I extract the vivado project from the 2019.2 BSP that I downloaded from Avnet, I get 2 PWM IPs that are locked because they are…

  • Ultra96-V2 getting started guide issues

    I've been using the Ultra96-V2 Getting Started Guide Version 1.1 to get started with the board and I'm running into some issues and some questions.

    Issue: No display when powering up and connecting the board to a display.
    - the display is an AOC…

  • Basic bare metal hardware design and software application missing for U96v2

    Hello,

    I have been using Xilinx tools (Vivado 2018-2019.1, SDK, Petalinux tools)  for previous Zynq7000 projects but in my current project we are using Zynq Ultrascale+ MPSoC.
    We bought an Ultra96v2 dev board to test the chip that's going on the prototype…

  • Problem getting USB running on Ultra96 v2 under UBUNTU 16.04.LTE VM

    Hello All, I am having trouble getting both my USB to work and my SDK to connect to my ULTRA96-v2 board under the UBUNTU 16.04 LTE VM,

     

    I refer to the following course document:  MPSoC_HW_2018_3_lab_2_v01_u96.pdf

    and specifically to LAB 2 Experiment 4,

     

    Page…

  • Disabling Bluetooth/WIFI

    We need to physically disable the Bluetooth/WIFI capability on the Ultra96 due to security requirements.
    Options we are considering:

    1. Cutting pin 19 (chip enable) on the ATWILC3000 module and tying it to ground
    2. Completely removing the ATWILC3000 module

    Has…

  • Does using Vitis with the Ultra96 really require 32GB of host memory?

    I've been following the newly released Vitis toolset and thought I'd give it a try.   Unfortunately it specifies a minimum requirement of 32GB of system memory with 64GB recommended.  Does anyone know if this requirement holds for smaller parts like…

  • Ultra96-V2 Vitis AI and DPU Support

    Hello Team,

     

    When do we expect the Ultra96-v2 board support within Vitis AI platform context. More specifically:

    i) Is the board supported in the vitis-ai-docker-runtime-image to allow cross-compilation?

    ii) Is there a working/release version of DPU image…

  • PL-PS configuration in Ultra96 v2

    Hello,

     

    With ultra96-v1 I can establish PS-PL axi interconnection and transfer processed data from PL to PS DDR, but no luck with Ultra96-V2.

     

    I have changed the PS DDR configuration according to

    LPDDR4 Memory differences between Ultra96-V1 and Ultra96-V2