Can someone explain what xilinx supports in terms of debug via coresight and how to access it?
While the ETB, PTM, ITM are in the CoreSign architecture and xilinx has added an AXI monitor and FTM, other than the AXI monitor, its not clear if the Xilinx tools (SDK/Chipscope) can take advantage and use the ETB, PTM, ITM and FTM.
1. How do the tools use these currently?
2. Must we purchase 3rd party tools to fully exploit these?
3. ARe they accessable thru SW APIs and JTAG via DAP using SDK/Chipscope?