I'm working on Tutorial:Ubuntu on the Zynqu2122 - 7000 SoC Featuring the Avnet ZedBoard
http://www.zedboard.org/sites/default/files/design/Ubuntu_on_Zedboard_Tutorial_v14.4_02.pdf
in Experiment 1 of Lab 1, I download Zed HDL Reference Design (cf_adv7511_zed_edk_14_4_2013_02_05.tar.gz) and Generate Bitstream in Xilinx Platform Studio (Step 4), it shows some error messages.
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Writing HDL for elaborated instances ...
Inserting wrapper level ...
Completion time: 1.00 seconds
Constructing platform-level connectivity ...
Completion time: 1.00 seconds
Writing (top-level) BMM ...
Writing (top-level and wrappers) HDL ...
Generating synthesis project file ...
Running XST synthesis ...
INFO:EDK:4211 - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
INSTANCE:axi_vdma_0 - C:cf_adv7511_zedsystem.mhs line 142 - Running XST
synthesis
PMSPEC -- Overriding Xilinx file <C:/Xilinx/14.4/ISE_DS/EDK/zynq/data/zynq.acd>
with local file <C:/Xilinx/14.4/ISE_DS/ISE/zynq/data/zynq.acd>
ERROR:Xst:2647 - Failed to run core generator for <system_axi_vdma_0_wrapper_fifo_generator_v9_1_2> macro.
ERROR:EDK:546 - Aborting XST flow execution!
INFO:EDK:2246 - Refer to
C:cf_adv7511_zedsynthesissystem_axi_vdma_0_wrapper_xst.srp for details
Running NGCBUILD ...
INFO:EDK:3509 - NCF files should not be modified as they will be regenerated.
If any constraint needs to be overridden, this should be done by modifying
the data/system.ucf file.
Rebuilding cache ...
ERROR:EDK:440 - platgen failed with errors!
make: *** [implementation/system_axi_vdma_0_wrapper.ngc] Error 2
Done!
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I found this solution
http://www.xilinx.com/support/answers/20780.htm
but the problem still there.
Test environment
OS:Windows 7 64bit and Windows XP SP3 32bit
Memory: 8GB
version of Xilinx ISE Deisgn Suite: 14.4