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Using Xilinx Tools Forum Error building U96_avnet Matrix Multiply Project
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Error building U96_avnet Matrix Multiply Project

mdouglas@verathon.com
mdouglas@verathon.com over 3 years ago

I am following one of the reference tutorials

(Tools 2018.2, Training Version v3, 18 Aug 2018)

This is in Lab 1, Experiment 2 Creating the Matrix Multiply Project for u96_avnet. I am following this to the letter except for choosing the u96_avnet platform instead of the mz_avnet platform. I get the errors below. Could this be an issue in the harware platform from avnet or the Xilinx Matrix Multiply template, or the SDSoC tool (2018.2)?

Any clue? Errors below (either Debug or Release, same results). Thanks!

C:\Users\MDouglas\workspace3\U96MM\Release>exit /b 0 
INFO: [PragmaGen 83-3231] Successfully generated tcl script: C:/Users/MDouglas/workspace3/U96MM/Release/_sds/vhls/mmult_accel.tcl
Moving function mmult_accel to Programmable Logic
ERROR: [SdsCompiler 83-5031] Problem detected in Vivado HLS run - unable to find solution implementation directory for mmult_accel C:/Users/MDouglas/workspace3/U96MM/Release/_sds/vhls/mmult_accel/solution/impl/ip. For possible causes, review C:/Users/MDouglas/workspace3/U96MM/Release/_sds/vhls/mmult_accel/solution/solution.log or C:/Users/MDouglas/workspace3/U96MM/Release/_sds/vhls/mmult_accel_vivado_hls.log.
C:/Users/MDouglas/workspace3/U96MM/Release/_sds/vhls/mmult_accel_vivado_hls.log (last 20 lines):
INFO: [HLS 200-10] Creating and opening project 'C:/Users/MDouglas/workspace3/U96MM/Release/_sds/vhls/mmult_accel'.
INFO: [HLS 200-10] Adding design file 'C:/Users/MDouglas/workspace3/U96MM/src/mmult.cpp' to the project
INFO: [HLS 200-10] Creating and opening solution 'C:/Users/MDouglas/workspace3/U96MM/Release/_sds/vhls/mmult_accel/solution'.
INFO: [HLS 200-10] Cleaning up the solution database.
INFO: [HLS 200-10] Setting target device to ' xczu3eg-sbva484-1-e '
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 2.7ns.
INFO: [HLS 200-10] Analyzing design file 'C:/Users/MDouglas/workspace3/U96MM/src/mmult.cpp' ... 
invalid command name "log_puts_err"
    while executing
"source C:/Users/MDouglas/workspace3/U96MM/Release/_sds/vhls/mmult_accel_run.tcl"
    invoked from within
"hls::main C:/Users/MDouglas/workspace3/U96MM/Release/_sds/vhls/mmult_accel_run.tcl -l mmult_accel_vivado_hls.log"
    ("uplevel" body line 1)
    invoked from within
"uplevel 1 hls::main {*}$args"
    (procedure "hls_proc" line 5)
    invoked from within
"hls_proc $argv"
INFO: [Common 17-206] Exiting vivado_hls at Thu Sep 13 14:01:15 2018...
sds++ log file saved as C:/Users/MDouglas/workspace3/U96MM/Release/_sds/reports/sds_mmult.log
ERROR: [SdsCompiler 83-5004] Build failed
 
make: *** [src/mmult.o] Error 1
 
14:05:13 Build Finished (took 4m:49s.180ms)
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  • bhfletcher
    0 bhfletcher over 3 years ago

    Marion,

      Were you able to get this working? I know there is a bug in SDSoC where the ACP is not an allowed resource. Once it is removed, then it will work. 

    We have instructions posted now at http://ultra96.org/support/design/24166/156 

    Ultra96 SDSoC Platform for v2018.2 (baremetal with Xilinx Matrix Multiple Example updated for Ultra96v1 BDF)

     

    Bryan

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  • mdouglas@verathon.com
    0 mdouglas@verathon.com over 3 years ago in reply to bhfletcher

    Hi Byan,

     

    Thanks for your reply. I just tried it. What is the ACP? I downloaded al the new stuff and re-ran froim scratch.

     

    Unfortunately, still the same issue:

     

    ...

    INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
    INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 2.7ns.
    INFO: [HLS 200-10] Analyzing design file 'C:/Avnet/SDx_workspace2/U96V1MM/src/mmult.cpp' ... 
    invalid command name "log_puts_err"
        while executing
    "source C:/Avnet/SDx_workspace2/U96V1MM/Debug/_sds/vhls/mmult_accel_run.tcl"
        invoked from within
    "hls::main C:/Avnet/SDx_workspace2/U96V1MM/Debug/_sds/vhls/mmult_accel_run.tcl -l mmult_accel_vivado_hls.log"
        ("uplevel" body line 1)
        invoked from within
    "uplevel 1 hls::main {*}$args"
        (procedure "hls_proc" line 5)
        invoked from within
    "hls_proc $argv"
    INFO: [Common 17-206] Exiting vivado_hls at Fri Oct 26 13:58:46 2018...
    sds++ log file saved as C:/Avnet/SDx_workspace2/U96V1MM/Debug/_sds/reports/sds_mmult.log
    ERROR: [SdsCompiler 83-5004] Build failed
     
    make: *** [src/mmult.o] Error 1
     
    14:02:41 Build Finished (took 4m:51s.430ms)
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  • mdouglas@verathon.com
    0 mdouglas@verathon.com over 3 years ago in reply to bhfletcher

    Hi Byan,

     

    Thanks for your reply. I just tried it. What is the ACP? I downloaded al the new stuff and re-ran froim scratch.

     

    Unfortunately, still the same issue:

     

    ...

    INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
    INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 2.7ns.
    INFO: [HLS 200-10] Analyzing design file 'C:/Avnet/SDx_workspace2/U96V1MM/src/mmult.cpp' ... 
    invalid command name "log_puts_err"
        while executing
    "source C:/Avnet/SDx_workspace2/U96V1MM/Debug/_sds/vhls/mmult_accel_run.tcl"
        invoked from within
    "hls::main C:/Avnet/SDx_workspace2/U96V1MM/Debug/_sds/vhls/mmult_accel_run.tcl -l mmult_accel_vivado_hls.log"
        ("uplevel" body line 1)
        invoked from within
    "uplevel 1 hls::main {*}$args"
        (procedure "hls_proc" line 5)
        invoked from within
    "hls_proc $argv"
    INFO: [Common 17-206] Exiting vivado_hls at Fri Oct 26 13:58:46 2018...
    sds++ log file saved as C:/Avnet/SDx_workspace2/U96V1MM/Debug/_sds/reports/sds_mmult.log
    ERROR: [SdsCompiler 83-5004] Build failed
     
    make: *** [src/mmult.o] Error 1
     
    14:02:41 Build Finished (took 4m:51s.430ms)
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