Zynq PS IP Core Ethernet Doesn't Come Up

RE: Zynq PS IP Core Ethernet Doesn't Come Up

Former Member — Wed, 24 Jun 2015 18:22:04 GMT

Hi Ron,
The original FSBL I was using I generated for my hardware using SDK. I did do some more digging and found that in fact the latest u-boot can generate a working build using the "foreign" FSBL. The "native" FSBL I was using was what was causing the failures. I rebuilt the FSBL, which as an aside took forever as my Vivado SDK decided it wanted to go ahead and corrupt itself, but I could still run the build through the command line. The re-generated FSBL also works. I'm not sure why the original FSBL wasn't working. Thanks for the insight, though, it was very helpful in trying to understand why this didn't work.
-Austin

RE: Zynq PS IP Core Ethernet Doesn't Come Up

Former Member — Wed, 24 Jun 2015 14:56:51 GMT

Austin,

The FSBL sets numerous device registers to set up the Zynq PS, so in general you should always make sure you generate the correct FSBL for a specific design, and not just copy it from another project. Since the Ethernet is part of the hard-core, I'm not saying another FSBL won't work (obviously the ADI example does), but if you had any special configuration set up in the Vivado design these setting would not be passed on to a "foreign" FSBL. As for U-boot, it's job is to load the kernel and DTB into DDR and it may pass some kernel arguments to the Linux loader, but I'm not aware of anything that would affect the Ethernet (but if anyone is and can enlighten me, please do). U-boot itself usually tries to make contact with a DHCP server, so if was not working it could be a clue that the PHY was not operating correctly at U-boot startup, and that points the finger at the hardware design (or FSBL configuration).

It would be interesting to know which component was the culprit here. If you have time, try swapping them out for your original versions one at a time and see if you can isolate the error.

Glad you got it going.

Ron

RE: Zynq PS IP Core Ethernet Doesn't Come Up

Former Member — Wed, 24 Jun 2015 00:45:30 GMT

I had a bad fsbl.elf or a bad u-boot, but when I switched to the fsbl.elf/u-boot supplied by Analog Devices, the Ethernet works like a charm. I didn't think those could affect the Ethernet, also why just the Ethernet? Too weird, but bottom line got Ethernet and DMA working.

RE: Zynq PS IP Core Ethernet Doesn't Come Up

Former Member — Tue, 23 Jun 2015 19:03:27 GMT

I had tried implementing a DTS like that. I tried that again using your example.
It still didn't work, but that did eliminate the message regarding selecting
a phy driver, so that does seem to force it to default to the Marvell. It's still
not starting the ethernet clock. I've had the Ethernet come up with a 2014.2 build
if I use the project distributed by Analog Devices for their FMCOMMS2 board.
I've copied their block design into a new project, removed everything except the
PS7 IP and when I build that cleaned version, it fails in the same way it has been
failing. I'm certain at this point that my issue has something to do with project
settings or build environment settings and not devicetree or IP core settings.

RE: Zynq PS IP Core Ethernet Doesn't Come Up

Former Member — Mon, 22 Jun 2015 19:45:57 GMT

Hi Austin,

I'm not aware of any problems in particular with a standard Ethernet design on any Zynq devices (Zedboard included) migrating from the old tools to the current versions. There have been some problems with more complex designs, such as dual-ethernet, but that shouldn't apply here.

There is an example Ethernet Performace design posted for Zedboard that uses the 2014.4 tool release, and it works fine. I decompiled the DTB that is suppled with that, and it gave me the following source for the Ethernet. Perhaps you can compare this with your device tree entry and see if there is anything that leaps out. This was built using the xilinx open source Linux, so it should be applicable to your implementation.

Ron

eth@e000b000 {
           compatible = "xlnx,ps7-ethernet-1.00.a";
           reg = <0xe000b000 0x1000>;
           interrupts = <0x0 0x16 0x0>;
           interrupt-parent = <0x1>;
           phy-handle = <0x2>;
           xlnx,ptp-enet-clock = <0x69f6bc7>;
           xlnx,slcr-div0-1000Mbps = <0x8>;
           xlnx,slcr-div0-100Mbps = <0x8>;
           xlnx,slcr-div0-10Mbps = <0x8>;
           xlnx,slcr-div1-1000Mbps = <0x1>;
           xlnx,slcr-div1-100Mbps = <0x5>;
           xlnx,slcr-div1-10Mbps = <0x32>;
           #address-cells = <0x1>;
           #size-cells = <0x0>;

           phy@0 {
               compatible = "marvell,88e1510";
               device_type = "ethernet-phy";
               reg = <0x0>;
               marvell,reg-init = <0x3 0x10 0xff00 0x1e 0x3 0x11 0xfff0 0xa>;
               linux,phandle = <0x2>;
               phandle = <0x2>;
           };
       };