I am trying to build the out-of-box design myself, so I can modify it.
I tried to follow this guide, but cannot generate the bitstream using xilinx platform studio that came with ISE 14.4 (The version that was used in the guide). I get the following Error when generating the bitstream the Design, without making any changes:
Failed to run core generator for <system_axi_interconnect_2_wrapper_fifo_generator_v9_1_1> macro.
I cannot figure out why. Does anybody have an Idea what to do?
I would much rather use Vivado 2018.3, has somebody ported the out-of-box project so that it can be built with Vivado?
I am very inexperienced with Vivado as well, is there any easy way to replicate the project so I can use it with the digilent linux kernel?