Versal VE2302 Hardware - Recent Threads

VE2302 Development Kit Unboxing and Getting Started Article

iksevas — Tue, 17 Feb 2026 21:54:47 GMT

The VE2302 Development Kit is fully shipping to customers in March timeframe. Here is some fresh content by Adam Taylor of MicroZed Chronicles fame:

Unboxing video: https://www.linkedin.com/posts/adam-taylor-8a991713_a-quick-look-at-the-tria-avnet-ve2302-and-activity-7429498057848881152-4TsT?utm_medium=ios_app&rcm=ACoAAACcEJEBjSxghthLaJWPdZJUcziMx0Hd7JM&utm_source=social_share_send&utm_campaign=copy_link

Getting Started Article: https://www.adiuvoengineering.com/post/microzed-chronicles-ve2302-development-kit

Master User Constraint File Released today.

iksevas — Fri, 23 Jan 2026 22:35:06 GMT

The Master User Constraint File for the SOM/Development Kit were posted to the board website today. They can be found on the SOM page and on the Development Kit page.

http://avnet.me/ve2302-som

http://avnet.me/ve2302-dk

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

iksevas — Wed, 21 Jan 2026 15:55:07 GMT

Please review all of the available user guides (SOM, Carrier Card, as well as CC Design Guide). All pinning information and schematic snippets exist there. As mentioned previously we are working to post a master constraints file that will aid customers in building their own Vivado designs. This is due soon.

otherwise, for schematics you need to get with your local field engineering team for Avnet who can submit an official request for the schematics pdf.

Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

iksevas — Fri, 16 Jan 2026 17:56:52 GMT

Brand new forum covering the release of the VE2302 Development Kit and the Versal AI Edge VE2302 SOM by Avnet / Tria-Technologies. Please ask any questions you have here when you get the chance!

Available documents are at the product page websites:

http://avnet.me/ve2302-dk

http://avnet.me/ve2302-som

Documentation that is currently publicly available is at TECHNICAL DOCUMENTS tab on those web pages. Scroll / navigate around and you should find them.

There is a BDF (board definition file) posted to the Avnet Github: Avnet/bdf: Avnet Board Definition Files

There are also a couple of repositories covering the VE2302 OOB for HW and PETALINUX in the Avnet GITHUB. This design is used for the Getting Started Guide.

More reference designs will begin to be posted to the sites / repos as they become available.

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

kboal — Wed, 21 Jan 2026 15:12:49 GMT

Another request for schematics please. We need this information to determine I/O location constraints for our custom design that we are prototyping on this board and more broadly for when we integrate the SOM onto a custom board.

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

iksevas — Tue, 20 Jan 2026 20:17:45 GMT

I have never actually been asked to deliver an XPFM fle to someone. Specifically, we have not attempted to use the Out of Box XSA from Vivado to create a PLATFORM in Vitis. We specifically targeted Petalinux and apps from Linux.

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

iksevas — Tue, 20 Jan 2026 19:13:19 GMT

All information you seek is available in User Guide.

Using reference carrier card, MRMAC would probably need to target HSIO expansion interface I believe as other interfaces targeting the GTs map to the HDMI and SFPs.

Unfortunately, schematics are only available when you are working through Avnet related sales/field engineering team.

We will be posting a master constraint file which will have interfaces separated and IO associated from the SOM connectors to the available carrier card peripherals.

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

jhou — Tue, 20 Jan 2026 18:15:18 GMT

Thanks for responding. I installed your board files and created a Vivado project based on DK carrier platform. Vivado is now happy. Jtag sees ve2302 ok. But to go next step such as bringing up MRMAC, I need to know what clocks, pin positions, DDR components, GPIOs, it is importamt to have schematics in hand to assign ios and probe. I do not have your reference build.

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

smsommer — Tue, 20 Jan 2026 18:01:38 GMT

Do you have an Embedded Platform (.xpfm) available for Vitis for the out-of-box reference design?

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

jhou — Sun, 18 Jan 2026 17:44:38 GMT

Hi, can you also release schematics? I will need details of pin positions and ref clocks to bring up peripherals, not just board files.

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

iksevas — Sat, 17 Jan 2026 17:13:43 GMT

PNs:

AES-VE2302-DK-G for Development Kit

100-kits (SOM/Carrier Card) scheduled to arrive mid-March over don’t run into issues with PCB procurement.

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

dyessgg — Sat, 17 Jan 2026 14:55:15 GMT

I found it after clicking through 3 links. 29 Weeks and $1,850 for the development kit. Not a bad price for a Versal chip.

RE: Release of the VE2302 Development Kit and VE2302 SOM - Technical Documents

dyessgg — Sat, 17 Jan 2026 14:51:23 GMT

Pricing and availability?