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linux crash after PL load

Former Member

I have made a simple hardware design for the PL. I can load it with either JTAG or by cat'ing the file into xdevcfg. Once the hardware is loaded, it functions properly. Howver, all contact with the PS (running Linux) is gone. No terminal, no ethernet. Is it not possible to just load a bit file with no reference to the processor? Looking in the UCF there doesn't appear to be any reference to any processor specific IOs. I'm guessing that I need to route some PS dedicated pins to some specific hardware pins, but I would have thought that could be done without anything loaded into the PL at all. Any insight would be appreciated.

  • 0 in reply to Former Member

    Hi jeffallred,You must have read this document, "Zynq-7000 EPP Technical Reference Manual". In the page 32,it's to said 'there are two type of interfaces between the PL and the PS'.One is functional interfaces, the other is configuration signals. I don't know how do you connect your hardware design to PS, but if you don't use any functional interface, it's dangerous I think. My IPcore make by XPS works well, and Linux device driver works well too. It never causes the OS to crash.
    PS. If you haven't read the document you can search it in www.xilinx.com. 
    If you think I can help you, is welcome to sent me a message for e-mail.

  • 0

    If you want to run linux and a custom bit file on the PS then:
    1. boot Linux without any hardware ip in PS (no AXI based peripheral)
    2. after linux boots load bit file through jtag
    3. then run linux application by downloading elf file to linux file system using remote ARM run app.
    Note: This is only to test PS & PL independently.
    Ideally before Linux would start booting. all peripherals on PL should be ideally present. Does this make sense?

  • 0 in reply to Former Member

    I know this thread has been inactive for a long time, but I want to revive it.

    If I allow the FSBL to load the PL and then later reload the PL using JTAG I always get a Linux crash. I have even tried taking the standard bit files from the reference design and using them.

    I'm interested in two things: First, I want to be able to reconfigure the PL at will. And second, the process of placing the bit file into the image for the FSBL is a bit time consuming.

    Has anyone been able to reconfigure the PL under Linux without a crash?

  • 0

    When you load the program to the PL does the Diligent logo disapear from the display?  I have this proglem too, it's like linux crashes whenever I try to load a simple bit file, I've tried both ways of loading the file (jtag and usb) and neither work, I haven't tried loading it through the terminal yet. 

  • 0

    Did you ever solve this problem?  Part of me thinks that it is because whenever I load the bit files for the FPGA (PL) and PS i bypass the PS (ARM) in iMPACT because I can't find the correct configuration file.  I am assuming that this will do nothing at all to the currect configuration of the PS/arm processor but it could be that programming in any way resets everything and that in order to have linux be reloaded it must be set in the configuration under the ARM PROCESSOR portion of the JTAG chain in iMPACT or whatever else you may be using to program it.

  • 0

    Although the claim is that the PS and PL are independent, my intuition tells me that isn't the case.  Booting with Linux requires a device tree binary file on the SD card so that the OS can know which peripherals are defined, their addresses, etc.  It uses that information to load and run drivers.  The peripheral addresses seem to be defined within XPS.  If I change the addresses in XPS, build a new bitstream and load it, wouldn't I reasonably expect Linux to have a fit?  Additionally, if there are any drivers actively talking to hardware, and the PL goes through a reset at the start or completion of the bitstream load, wouldn't I reasonably expect the OS to experience an AXI bus error?  The idea that the PS and PL are independent doesn't seem like it is possible to me.

  • 0

    Bump

    I'm running a QNX port to the Zedboard (from a ZC702 version). I have a PL configuration file that uses the GP and ACP interfaces for interrupts and reading values from some BRAM using a CDMA.

    Everything runs great when I boot and the FSBL configures the logic. If I try and reconfigure the PL with the exact same PL configuration (bin file instead of a bit file), QNX still runs fine. But as soon as I try to access anything over the AXI, the whole system hangs as described above.

    Does anyone have any insight to this? Could it be a problem with the silicon revision shipped with the Zedboard...? I haven't seen anyone else describing this scenario on other forums except for a random errata case when you try and access OCM and DDR from the PL at the same time (which I'm not doing).

    Looking at the FSBL code compared to the Linux and QNX PL drivers, there seems to be a PL "initialization" that happens at boot. I'm wondering if something like that might be necessary when reconfiguring...

    I guess it could also be a problem with my PL design. Maybe a reset isn't going to every piece from the PS, so the PL is cranking away while the PS tries to reconfigure the PL. I wouldn't think this would result in a system crash, but this new kind of SoC has some strange quirks to it.

    Anyone else make any progress?

  • 0 in reply to Former Member

    I just found this forum discussion:

    http://forums.xilinx.com/t5/Embedded-Linux/Zynq-Loading-bitfile-into-FPGA-from-Linux-xdevcfg/m-p/237872#M4062

    Sounds similar to what we're describing. I've been using the promgen method so I'm going to double check my command options. If there's nothing there, I'm going to try the bootgen method. I'll report back if I have any success.