Hello,
When I create a new IP using AXI Burst interface, XPS creates a vhdl file (myip.vhd) with some Xilinx modules :
- the axi_lite_ipif_v1_01_a.axi_lite_ipif, to communicate with GP ports through AXI_LITE
- the axi_master_burst_v1_00_a.axi_master_burst IP, to communicate with HP ports through AXI_BURST
The thing is it seems we can't configure the axi_master_burst with more than 128 bits for the width of the IPIC interface. It's indeed confirmed in the documentation ds844_axi_master_burst.pdf. However, it's possible to have an AXI interface of 256bits.
In the documentation they also show this schema ( https://www.dropbox.com/s/j4oejn8ieohe047/256bits_IPIC.png ).
Since the "Master IPIC" is at maximum 128bits, I don't understand why it is connected with 4 HP ports (256bits). 2 HP ports could be sufficient, right ?
When I implement this design, the max frequency is about 100MHz. It means that the maximum bandwidth is 1600 MB/s (128b*100MHz) for each way. It's not that bad for the 7020 chip but can be limitating for a bigger 7045 chip with more computing power.
Is there an easy way to have a 256bits width IPIC interface to benefit of the throughput of the 4x64bits HP port (256bits) ?
Thank you for reading
