Voltage divider on VREF for Ethernet interface

Why is there a voltage divider on PS_MIO_VREF on the Zed board schematics? UG933 indicates it needs to be there when using an HSTL18 RGMII interface (which I would expect) but the Zed board is connected to the PHY using LVCMOS18 so why would this be needed?

0 Former Member over 12 years ago

PS_ implies this is a ARM processor sub-system MIO pin function -- NOT the FPGA IOB. Thus, we follow the ARM rules for the PS pins.
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0 Former Member over 12 years ago in reply to Former Member

Thank you for the comment on this. Is there a particular piece of documentation you're referencing that indicates a voltage divider is required on these pins for ARM MIO functionality? I looked but didn't see any.
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0 Former Member over 12 years ago

I just follow the "rules:" one does not question why ARM says to do whatever they say....

If you wish to know what ARM does in their IP blocks, you need to get a license (and sign the NDA).
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0 Former Member over 12 years ago

I guess I'm asking what 'rules' you're following. The Zynq documentation, from what I can tell, doesn't indicate a voltage divider is needed on these pins. If I hadn't noticed this divider in the ZED schematics I wouldn't have known to connect it in this manner which is why I'm asking where in the Zynq documentation it is referenced.
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0 Former Member over 9 years ago in reply to Former Member

I know this is an old discussion, but just in case anyone else was searching for the answer, I found the details on the PS_MIO_VREF pin in ug865-Zynq-7000-Pkg-Pinout.pdf from Xilinx. In Table 1-5 I found the following description:

"The PS_MIO_VREF provides a reference voltage for the
RGMII input receivers.

If an RGMII interface is not being used, the PS_MIO_VREF
pin can be left to float.

If an RGMII interface is being used, tie this pin to a voltage equal to u00BD VCCO_MIO1."
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