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error exporting design into SDK

Former Member

Hi,
I tried following the design example for 2013.2 for the zedboard in Reference Designs/Tutorials: Zynq Concepts, Tools, and Techniques on ZedBoard

I am using vivado 2013.4

I got to page 22 of the instruction where it says to do a file export but I get this error:

export_hardware [get_files C:/My_Designs/zyncTest/zyncTest1/zyncTest1.srcs/sources_1/bd/system/system.bd]
ERROR: [BD 41-440] Hardware design cannot be exported until the IP Integrator design has been generated
ERROR: [Common 17-39] 'export_hardware' failed due to earlier errors.

I did notice that when vivado created the wrapper file, it did not create an constraints for the pins so I am wondering if the system is not set correctly to begin with. Any help would be highly appreciated.
Thanks,
Amish

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  • 0 in reply to Former Member

    The Vivado tools do generate constraints for the portions of the design it 'knows about' from the 'Board Presets' you set earlier. These pin location, IO Standards, etc. are just not put in the upper level xdc constraints file you use. They are buried in another xdc constraints file that is picked up by the tools as needed. If you want to see them do a search for .xcd file types within your project sub-directories.

     

    You only need to specify the constraints it cannot imply from the board preset, things like the Pin locations and IO Standard assignments for I/O connected to the Programmable Logic (PL) section.

     

    -Gary