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ZedBoard Hardware Design QSPI Size Limit /Type for Zynq
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QSPI Size Limit /Type for Zynq

Former Member
Former Member over 12 years ago

Reading through the ug585-Zynq-7000-TRM.pdf, I note from section 12 that the Quad-SPI Flash Controller cannot address more than 16 MBytes, or use flash greater than 128 Mbit. Yet, the Zedboard comes with a 256 Mbit QSPI flash. Why?

Is there something I'm missing, or does the Zedboard waste half of its QSPI flash?

Also, the QSPI chips look to be NOR flash generally, such as for the S25FL128SAGNFI001, the (proper?) smaller version of the flash used in the Zedboard. But on pages 49-50 of the same TRM above, the 7z010 CLG225 device is said to have no NOR/SRAM interfacing. Yet, with this smaller Zynq device set in Vivado, I can nevertheless choose the Quad SPI Flash for MIO pins 1-6 (Quad SPI 0).

Is this an exception to the NOR interfacing limitation for this smaller Zynq device, or do I need to use a NAND type QSPI chip for this smaller Zynq?

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  • Former Member
    0 Former Member over 12 years ago

    Got a response from the Xilinx forum. The following link adds clear emphasis that the UG585 is correct. So Zynq boards like the Zedboard are wasting a lot of the QSPI memory by using excessively large 256 Mbit chips.

    www.xilinx.com/support/answers/47500.html

    It doesn't definitively answer the conflicting information in UG585, that says QPSI drivers are not possible for NOR flash with the smaller 225 pin Zynq chips. But the term "hardened QSPI controller" would indicate the driver is probably the same between larger and smaller pin out chips. As such, the 7z010 CLG225 device is probably indeed capable of using the usual NOR QPSI chips. I'll find out when I make my board.

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  • Former Member
    0 Former Member over 12 years ago

    Software needs to set a register in the SPI chip to bank swap in the rest of the memory. See the Quad-SPI chip data sheet for details. 

    The app note is correct, but only if you consider direct access without this bank swapping.

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