In our design, we have an streaming peripheral connected to the S2MM channel of the AXI_VDMA in order to send data from PL to DDR.
We have monitored the M_AXI_GPx channel with Chipscope checking that the VDMA is initialized without problems. However, monitoring the S_AXI_HPx channel, we have observed that any data are sent to the DDR.
This is our system.mhs:
PARAMETER VERSION = 2.1.0
PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
PORT processing_system7_0_PS_SRSTB_pin = processing_system7_0_PS_SRSTB, DIR = I
PORT processing_system7_0_PS_CLK_pin = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
PORT processing_system7_0_PS_PORB_pin = processing_system7_0_PS_PORB, DIR = I
PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
BEGIN processing_system7
PARAMETER INSTANCE = processing_system7_0
PARAMETER HW_VER = 4.03.a
PARAMETER C_DDR_RAM_HIGHADDR = 0x1FFFFFFF
PARAMETER C_EN_EMIO_CAN0 = 0
PARAMETER C_EN_EMIO_CAN1 = 0
PARAMETER C_EN_EMIO_ENET0 = 0
PARAMETER C_EN_EMIO_ENET1 = 0
PARAMETER C_EN_EMIO_I2C0 = 0
PARAMETER C_EN_EMIO_I2C1 = 0
PARAMETER C_EN_EMIO_PJTAG = 0
PARAMETER C_EN_EMIO_SDIO0 = 0
PARAMETER C_EN_EMIO_CD_SDIO0 = 0
PARAMETER C_EN_EMIO_WP_SDIO0 = 0
PARAMETER C_EN_EMIO_SDIO1 = 0
PARAMETER C_EN_EMIO_CD_SDIO1 = 0
PARAMETER C_EN_EMIO_WP_SDIO1 = 0
PARAMETER C_EN_EMIO_SPI0 = 0
PARAMETER C_EN_EMIO_SPI1 = 0
PARAMETER C_EN_EMIO_SRAM_INT = 0
PARAMETER C_EN_EMIO_TRACE = 0
PARAMETER C_EN_EMIO_TTC0 = 1
PARAMETER C_EN_EMIO_TTC1 = 0
PARAMETER C_EN_EMIO_UART0 = 0
PARAMETER C_EN_EMIO_UART1 = 0
PARAMETER C_EN_EMIO_MODEM_UART0 = 0
PARAMETER C_EN_EMIO_MODEM_UART1 = 0
PARAMETER C_EN_EMIO_WDT = 0
PARAMETER C_EN_EMIO_GPIO = 0
PARAMETER C_EMIO_GPIO_WIDTH = 64
PARAMETER C_EN_QSPI = 1
PARAMETER C_EN_SMC = 0
PARAMETER C_EN_CAN0 = 0
PARAMETER C_EN_CAN1 = 0
PARAMETER C_EN_ENET0 = 1
PARAMETER C_EN_ENET1 = 0
PARAMETER C_EN_I2C0 = 0
PARAMETER C_EN_I2C1 = 0
PARAMETER C_EN_PJTAG = 0
PARAMETER C_EN_SDIO0 = 1
PARAMETER C_EN_SDIO1 = 0
PARAMETER C_EN_SPI0 = 0
PARAMETER C_EN_SPI1 = 0
PARAMETER C_EN_TRACE = 0
PARAMETER C_EN_TTC0 = 1
PARAMETER C_EN_TTC1 = 0
PARAMETER C_EN_UART0 = 0
PARAMETER C_EN_UART1 = 1
PARAMETER C_EN_MODEM_UART0 = 0
PARAMETER C_EN_MODEM_UART1 = 0
PARAMETER C_EN_USB0 = 1
PARAMETER C_EN_USB1 = 0
PARAMETER C_EN_WDT = 0
PARAMETER C_EN_DDR = 1
PARAMETER C_EN_GPIO = 1
PARAMETER C_FCLK_CLK0_FREQ = 100000000
PARAMETER C_FCLK_CLK1_FREQ = 142857152
PARAMETER C_FCLK_CLK2_FREQ = 50000000
PARAMETER C_FCLK_CLK3_FREQ = 50000000
PARAMETER C_USE_CR_FABRIC = 1
PARAMETER C_USE_M_AXI_GP0 = 1
PARAMETER C_USE_S_AXI_HP0 = 1
PARAMETER C_INTERCONNECT_S_AXI_HP0_MASTERS = axi_vdma_0.M_AXI_MM2S & axi_vdma_0.M_AXI_S2MM
PARAMETER C_S_AXI_HP0_DATA_WIDTH = 32
PARAMETER C_INTERCONNECT_S_AXI_HP0_AW_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_HP0_AR_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_HP0_W_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_HP0_R_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_HP0_B_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_HP0_WRITE_FIFO_DEPTH = 512
PARAMETER C_INTERCONNECT_S_AXI_HP0_READ_FIFO_DEPTH = 512
PARAMETER C_INTERCONNECT_S_AXI_HP0_WRITE_FIFO_DELAY = 0
PARAMETER C_INTERCONNECT_S_AXI_HP0_READ_FIFO_DELAY = 0
PARAMETER C_INTERCONNECT_S_AXI_HP0_WRITE_ACCEPTANCE = 8
PARAMETER C_INTERCONNECT_S_AXI_HP0_READ_ACCEPTANCE = 8
BUS_INTERFACE M_AXI_GP0 = axi_interconnect_axi_lite
BUS_INTERFACE S_AXI_HP0 = axi_interconnect_axi_data
PORT MIO = processing_system7_0_MIO
PORT PS_SRSTB = processing_system7_0_PS_SRSTB
PORT PS_CLK = processing_system7_0_PS_CLK
PORT PS_PORB = processing_system7_0_PS_PORB
PORT DDR_Clk = processing_system7_0_DDR_Clk
PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
PORT DDR_CKE = processing_system7_0_DDR_CKE
PORT DDR_CS_n = processing_system7_0_DDR_CS_n
PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
PORT DDR_WEB = processing_system7_0_DDR_WEB
PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
PORT DDR_Addr = processing_system7_0_DDR_Addr
PORT DDR_ODT = processing_system7_0_DDR_ODT
PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
PORT DDR_DQ = processing_system7_0_DDR_DQ
PORT DDR_DM = processing_system7_0_DDR_DM
PORT DDR_DQS = processing_system7_0_DDR_DQS
PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
PORT DDR_VRN = processing_system7_0_DDR_VRN
PORT DDR_VRP = processing_system7_0_DDR_VRP
PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0
PORT S_AXI_HP0_ACLK = processing_system7_0_FCLK_CLK0
PORT S_AXI_HP0_ARESETN = processing_system7_0_S_AXI_HP0_ARESETN
PORT IRQ_F2P = axi_vdma_0_s2mm_introut & axi_vdma_0_mm2s_introut
END
BEGIN axi_vdma
PARAMETER INSTANCE = axi_vdma_0
PARAMETER HW_VER = 5.04.a
PARAMETER C_INCLUDE_MM2S = 1
PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 8
PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 8
PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 8
PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 8
PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 8
PARAMETER C_USE_FSYNC = 0
PARAMETER C_INCLUDE_S2MM_SF = 0
PARAMETER C_INCLUDE_MM2S_SF = 0
PARAMETER C_PRMRY_IS_ACLK_ASYNC = 1
PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 8
PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 8
PARAMETER C_S2MM_LINEBUFFER_DEPTH = 4096
PARAMETER C_S2MM_MAX_BURST_LENGTH = 16
PARAMETER C_MM2S_LINEBUFFER_DEPTH = 4096
PARAMETER C_MM2S_MAX_BURST_LENGTH = 16
PARAMETER C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH = 512
PARAMETER C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING = 8
PARAMETER C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DELAY = 1
PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 8
PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 8
PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 8
PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 8
PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 8
PARAMETER C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH = 512
PARAMETER C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DELAY = 1
PARAMETER C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING = 8
PARAMETER C_BASEADDR = 0x43000000
PARAMETER C_HIGHADDR = 0x4300ffff
BUS_INTERFACE S_AXI_LITE = axi_interconnect_axi_lite
BUS_INTERFACE M_AXI_MM2S = axi_interconnect_axi_data
BUS_INTERFACE M_AXI_S2MM = axi_interconnect_axi_data
BUS_INTERFACE S_AXIS_S2MM = sum_stream_0_M_AXIS
BUS_INTERFACE M_AXIS_MM2S = axi_vdma_0_M_AXIS_MM2S
PORT s_axi_lite_aclk = processing_system7_0_FCLK_CLK0
PORT m_axi_mm2s_aclk = processing_system7_0_FCLK_CLK0
PORT m_axi_s2mm_aclk = processing_system7_0_FCLK_CLK0
PORT m_axis_mm2s_aclk = processing_system7_0_FCLK_CLK0
PORT s_axis_s2mm_aclk = processing_system7_0_FCLK_CLK0
PORT s2mm_introut = axi_vdma_0_s2mm_introut
PORT mm2s_introut = axi_vdma_0_mm2s_introut
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_axi_lite
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END
BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_axi_data
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 1
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
END
BEGIN sum_stream
PARAMETER INSTANCE = sum_stream_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE M_AXIS = sum_stream_0_M_AXIS
BUS_INTERFACE S_AXIS = axi_vdma_0_M_AXIS_MM2S
PORT ACLK = processing_system7_0_FCLK_CLK0
END
BEGIN chipscope_icon
PARAMETER INSTANCE = chipscope_icon_0
PARAMETER HW_VER = 1.06.a
PARAMETER C_NUM_CONTROL_PORTS = 2
PORT control0 = chipscope_icon_0_control0
PORT control1 = chipscope_icon_0_control1
END
BEGIN chipscope_axi_monitor
PARAMETER INSTANCE = chipscope_axi_monitor_1
PARAMETER HW_VER = 3.05.a
BUS_INTERFACE MON_AXI = processing_system7_0.S_AXI_HP0
PORT CHIPSCOPE_ICON_CONTROL = chipscope_icon_0_control0
END
BEGIN chipscope_axi_monitor
PARAMETER INSTANCE = chipscope_axi_monitor_0
PARAMETER HW_VER = 3.05.a
BUS_INTERFACE MON_AXI = axi_vdma_0.M_AXI_S2MM
PORT CHIPSCOPE_ICON_CONTROL = chipscope_icon_0_control1
END
Is there something wrong or strange in the system design? Maybe more details are needed to find out the problem.
Thank you very much in advance.
Best regards,
Ainhoa