Hi all,
I am searching for a possibility to simulate custom IP Cores. I found a interesting solution with the "Hardware in the loop simulation" described here:
http://www.xilinx.com/support/documentation/application_notes/xapp744-HIL-Zynq-7000.pdf
But in this topic
(http://www.zedboard.org/content/zynq-hil-co-simulation-zedboard)
they said it wasn't possible with Zedboard last year, and I didn't found any information in the internet which say it is possible today...
So I tried to Simulate my IPs with the "Bus Functional Models"(BFM) but I found not much information how to do this correctly and have the problem that "Fuse.exe" doesn't work after generating the "Simulation HDL Files".
So have anyone of you experience with the BFM or do you know other(maybe better) possibilities to simulate IP Cores?
Thanks!