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To make PL bram/fifo writing through PS AXI_M_GP and read through PL in ISE top

Former Member

Hi all,

According to my requirement i need to make the FIFO/BRAM in PL(out of EDK) to be accessed by PS using Master GP port to write and to read the data from FIFO/BRAM through PL (Through ISE top).

I am trying out with various options like by using axi external slave interface... but i am unable to find the suitable solution to my requirement.

Can anybody suggest the solution/any design example that suits my requirement.

 

Thanks in advance. 

  • 0

    Hello,

    It looks like you are attempting to use the older Xilinx ISE tool suite. I would strongly suggest that you move your project to the current Xilinx Vivado tool suite for better support and results. The free WebPack version of the Vivado tools is all that you will need to develop on the ZedBoard.

    The Avnet Zynq Hardware Speedway tutorial would be a good place to start. In lab 5 there is an example of implementing a BRAM in the PL connected to the PS using an AXI BRAM controller. If you configured the BRAM to be a dual port memory you could then connect your custom PL logic to the other BRAM port. Lab 7 of the Speedway tutorial has an example of implementing your own custom IP block. The Speedway material can be downloaded here:

    http://zedboard.org/support/trainings-and-videos

    Adam Taylor also has a very good blog on developing projects using the Zynq processor. There is a 7 part series, starting with chapter 21, on creating your own custom AXI peripheral.

    http://zedboard.org/content/microzed-chronicles

    There are also some good tutorials and example designs on the Xilinx website as well.

    -Gary