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Interface custom VHDL code with PS simple_register

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I followed the instructions to create custom peripheral simple_register. I am able to read and write values to my register.

I am now interested in connecting my VHDL entity to the simple_register inside the PS.
e.g my VHDL entity has:

entity fpga1_top_fp is
    Port (
    --! Inputs
    clk                 : in std_logic; --! clock input
    rst                 : in std_logic; --! reset
    ce                  : in std_logic; --! enable
    ndata_en            : in std_logic; --! new data enable
    ia                  : in std_logic_vector(31 downto 0);
    --! Outputs
    va                  : out std_logic_vector(31 downto 0)
    ) ;
end entity fpga1_top_fp;

Now I connect this in user_logic.vhd:
uut: fpga1_top_fp PORT MAP(
clk => Bus2IP_Clk,
rst => slv_reg0(0),
ce => slv_reg0(1),
ndata_en => slv_reg0(2),
ia => slv_reg1,
va => slv_reg2);

I have instantiated my simple_register with 16 registers and I am using slv_reg0 to set my handshaking signals. slv_reg1 is a write register and slv_reg2 is a read register.

Qns:
1. How do I add fpga1_top_fp to my synthesis path through planahead?
2. The workaround I did was to synthesize and implement my fpga1_top_fp using ISE and then copy the .ngc files and the coregen .ngc files to the .srcs/edk/implementation folder. Still I see Translate error when using PlanAhead to implement my design.
Errors:
a. BUffers of the same direction cannot be placed in series,
b. FCLK_CLK0 is driving non-buffer primitives

Any suggestions or pointers to start troubleshooting?

Thanks in advance !!

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    When you generate the VHDL template there should be ports which you have made external in XPS.  In the hardware tutorial at 2-4 they make the GPIO_LED_8bits external so it will now appear in the instantiation template.

    The simple_register is in the same position as the GPIO IP connected to the interconnect and your VHDL entity should be connected in the same way their debouncer.vhd file is.  (The files for the tutorial are located in the support directory in case you hadn't already found them)

    It might be possible to connect the entity as you were trying to in your original post, but you would need to edit the .pao files for your custom peripheral.  I think the way they do it is much easier to follow.

    So in summary:
    1. In XPS, Create your custom peripheral using the wizard
    2. Create the ports to connect that peripheral to your VHDL entity
    3. Rescan User Repositories and connect the ports as external
    4. In PlanAhead, Generate the top level VHDL (it should have ports for your peripheral because you made them external)
    5. Instantiate your VHDL entity as a component in the top level and connect it to the ports
    6. Sythesize, Implement, Generate Bitstream

    Hope that clears things up, if you need a further look at connecting additional ports to user_logic.vhd Chapter 9 of UG873 gives an example for a counter connected to the LEDs, but most of the steps are referenced from Chapter 6 of the EDK CTT after the in-depth look at the wizard.  Links Below:

    UG873
    http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/ug873-zynq-ctt.pdf

    EDK CTT
    http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/edk_ctt.pdf

    Matthew

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  • 0

    When you generate the VHDL template there should be ports which you have made external in XPS.  In the hardware tutorial at 2-4 they make the GPIO_LED_8bits external so it will now appear in the instantiation template.

    The simple_register is in the same position as the GPIO IP connected to the interconnect and your VHDL entity should be connected in the same way their debouncer.vhd file is.  (The files for the tutorial are located in the support directory in case you hadn't already found them)

    It might be possible to connect the entity as you were trying to in your original post, but you would need to edit the .pao files for your custom peripheral.  I think the way they do it is much easier to follow.

    So in summary:
    1. In XPS, Create your custom peripheral using the wizard
    2. Create the ports to connect that peripheral to your VHDL entity
    3. Rescan User Repositories and connect the ports as external
    4. In PlanAhead, Generate the top level VHDL (it should have ports for your peripheral because you made them external)
    5. Instantiate your VHDL entity as a component in the top level and connect it to the ports
    6. Sythesize, Implement, Generate Bitstream

    Hope that clears things up, if you need a further look at connecting additional ports to user_logic.vhd Chapter 9 of UG873 gives an example for a counter connected to the LEDs, but most of the steps are referenced from Chapter 6 of the EDK CTT after the in-depth look at the wizard.  Links Below:

    UG873
    http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/ug873-zynq-ctt.pdf

    EDK CTT
    http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_3/edk_ctt.pdf

    Matthew

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