I followed the instructions to create custom peripheral simple_register. I am able to read and write values to my register.
I am now interested in connecting my VHDL entity to the simple_register inside the PS.
e.g my VHDL entity has:
entity fpga1_top_fp is
Port (
--! Inputs
clk : in std_logic; --! clock input
rst : in std_logic; --! reset
ce : in std_logic; --! enable
ndata_en : in std_logic; --! new data enable
ia : in std_logic_vector(31 downto 0);
--! Outputs
va : out std_logic_vector(31 downto 0)
) ;
end entity fpga1_top_fp;
Now I connect this in user_logic.vhd:
uut: fpga1_top_fp PORT MAP(
clk => Bus2IP_Clk,
rst => slv_reg0(0),
ce => slv_reg0(1),
ndata_en => slv_reg0(2),
ia => slv_reg1,
va => slv_reg2);
I have instantiated my simple_register with 16 registers and I am using slv_reg0 to set my handshaking signals. slv_reg1 is a write register and slv_reg2 is a read register.
Qns:
1. How do I add fpga1_top_fp to my synthesis path through planahead?
2. The workaround I did was to synthesize and implement my fpga1_top_fp using ISE and then copy the .ngc files and the coregen .ngc files to the .srcs/edk/implementation folder. Still I see Translate error when using PlanAhead to implement my design.
Errors:
a. BUffers of the same direction cannot be placed in series,
b. FCLK_CLK0 is driving non-buffer primitives
Any suggestions or pointers to start troubleshooting?
Thanks in advance !!
