Hello,
I would like to be able write to the DDR memory from the PL in a simple fashion, something like this: clock data into a FIFO which is stored directly into DDR memory that the PS can retrieve at its leisure. I understand that there are several AXI IP blocks that can help me with this and that UG873 gives an example of using an AXI block to transfer memory from one DDR address to another.
What I am looking for help on is interfacing my programmable logic to the AXI blocks to begin with. Is there a simple FIFO block which will let me clock data into it (not using AXI, just using a FIFO_WRITE port) and then expose FIFO_READ via an AXI interface that can be connected to one of the AXI DMA blocks? In otherwords, is there anyway to do what I want to do without having to write a verilog AXI master device?
Thanks!
Eric