I am using a MiniZed Zedboard
I have been having issues getting the clocks from the Zynq processing system to reach my FPGA HDL design. I ran into this same issue on another personal project, something small, and found some late-night solution that I have been unable to reproduce on this new, also very simple, project.
Basically, I can't seem to get the FCLK_CLK1 to reach the input of my RTL "sys_clk" . I know this interface is supposed to be handled by some sort of wrapper code generated by Vivado, but I generated the wrapper to the block diagram and it is throwing this error. Its some sort of issue with how the software handles the interface between the processing system and RTL(via the HDL wrapper) so I am at an end on what to do.
Here is a picture of my Vivado interface with my block diagram shown, and the error code at the bottom.
I have done a lot of searching and haven't found any other issues describing this.
The design was synthesizable and could be ported onto the board before I had to add clocking "sys_clk" and "rst" signals (interface it with the zynq processing system). I havent found any guides on how to properly do this.
Any help would be greatly appreciated.
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