ZedBoard Hardware Design - Recent Threads

Vivado BRAM Instantiation Issues

dniemann17 — Tue, 24 Jun 2025 14:39:07 GMT

Hello!

We are currently working on a project which requires us to extend a previously created memory interface on a ZedBoard from being 4k in size to 256k (A 1/4 of a MB).
We had previously created a file, called pocket_core_top_mem.v which instantiated a 4k long memory (4 xilinx_tdpram_1024x36 modules) that has been working for the longest time. This old interface used only 4 blocks of 140 available Block RAM modules on the zedboard for the project (50 blocks are used elsewhere, leaving 86 remaining).
community.element14.com/.../pocket_5F00_core_5F00_top_5F00_mem.v.txt
While doing this, we simply started by trying to nest multiple memory files (using xilinx_tdpram_1024x36 modules), where we would have a .v file and module for 16k ram (4 4k modules), a file for 64k ram (4 16k modules), and finally a top file which consisted of 4 64k modules. (called pocket_core_mem_16k.v, pocket_core_mem_64k.v, and pocket_core_top_mem_nested.v here).
community.element14.com/.../pocket_5F00_core_5F00_mem_5F00_16k.v.txt community.element14.com/.../pocket_5F00_core_5F00_mem_5F00_64k.v.txt community.element14.com/.../pocket_5F00_core_5F00_top_5F00_mem_5F00_nested.v.txt
Unfortunately, when we went to build the project, it ran through with no errors and wrote the bitstream but unfortunately only 2 RAM blocks were instantiated in the implemented design and I was only able to read and write to 0x100 of the memory space I programmed in. In Vivado, it was only reporting that 51 of the 140 RAM blocks were instantiated.
So, I then created and ran a simulation in Icarus Verilog on my files to see if I could indeed read and write to the higher address blocks. This simulation worked and proved my files didn't have a design error.

I was dumbstruck and thought it was how Vivado interpreted my file methodology that was making the error occur. So, I then simply made a single file (named pocket_core_top_mem_single.v here) with 64 xilinx_tdpram_1024x36 modules in it.
This STILL only had 2 RAM blocks instantiated when Vivado finished building and writing the bitstream:

I also ran simulations to confirm if this file worked or not, and they confirmed the file worked.
community.element14.com/.../pocket_5F00_core_5F00_top_5F00_mem_5F00_single.v.txt

Would there be anything that could be preventing Vivado from instantiating these 64 BRAM blocks that I may have missed?

Regards,
Daniel

Configure core0 with petalinux and core1 baremetal on Zedboard 2018.3

caferba — Tue, 29 Apr 2025 12:04:18 GMT

Hello,

I am working with the Zedboard 2018.3 Rev F and I'm having issues when trying to launch an application on CPU1 from petalinux 2018.3 on CPU0. After loading the firmware and starting nothing happens. It seems that the baremetal application on cpu1 is not starting. I have followed the UG1186 documentation for A9-zynq platforms.

root@avnet-digilent-zedboard-2018_3:/lib/firmware# echo hello-linux.elf > /sys/class/remoteproc/remoteproc0/firmware

root@avnet-digilent-zedboard-2018_3:/lib/firmware# echo start > /sys/class/remoteproc/remoteproc0/state

remoteproc remoteproc0: powering up remoteproc@0

remoteproc remoteproc0: Booting fw image hello-linux.elf, size 2534900

remoteproc remoteproc0: registered virtio0 (type 7)

remoteproc remoteproc0: remote processor remoteproc@0 is now up

root@avnet-digilent-zedboard-2018_3:/lib/firmware# virtio_rpmsg_bus virtio0: rpmsg host is online

system-user.dtsi:

/include/ "system-conf.dtsi"

/ {

chosen

{

bootargs = "uio_pdrv_genirq.of_id=generic-uio";

};

/ {

reserved-memory {

#address-cells = <1>;

#size-cells = <1>;

ranges;

vdev0vring0: vdev0vring0@3e800000 {

no-map;

compatible = "shared-dma-pool";

reg = <0x3e800000 0x4000>;

};

vdev0vring1: vdev0vring1@3e804000 {

no-map;

compatible = "shared-dma-pool";

reg = <0x3e804000 0x4000>;

};

vdev0buffer: vdev0buffer@3e808000 {

no-map;

compatible = "shared-dma-pool";

reg = <0x3e808000 0x100000>;

};

rproc_0_reserved: rproc@3e000000 {

no-map;

reg = <0x3ed00000 0x00400000>;

};

amba {

elf_ddr_0: ddr@0 {

compatible = "mmio-sram";

reg = <0x3e000000 0x400000>;

};

remoteproc0: remoteproc@0 {

compatible = "xlnx,zynq_remoteproc";

firmware = "firmware";

vring0 = <15>;

vring1 = <14>;

srams = <&elf_ddr_0>;

};

Thank you

Carlos

Connecting Zedboard to Vivado - Hardware Manager not Detecting

eb_air — Fri, 21 Mar 2025 19:12:04 GMT

Hello,

I have been struggling to detect my Zedboard on Vivado's Hardware Manager run in a Linux OS. When I went into the Hardware Manager, I could connect into the local hardware server, but the Zedboard did not show up. I used version 2023.2 and 2022.2, but both versions had the same problem. I tried the JTAG and UART modes with no success. I am confused with the problem here because if I run lsusb, I see "232H Single HS USB-UART/FIFO IC" for the JTAG interface and "Cypress Semiconductor Corp. CDC ACM serial port", which I assume means the drivers are properly installed.

Is there something I am doing wrong here?

Je1 GPIO - Cant seem to access upper pins

PurplePig — Fri, 14 Mar 2025 11:33:58 GMT

# Xilinx Zedboard (Zynq 7020) GPIO 0

I am working with a new Zedboard with the Zynq 7020 processor.

I was trying to strobe the pins on the JE1 PMOD port

To this end I defined the following pins

```

File: helloworld.c

61: int iPortPins[10];

62:

63: #define JE1 13

64: #define JE2 10

65: #define JE3 11

66: #define JE4 12

67: #define JE7 0

68: #define JE8 9

69: #define JE9 14

70: #define JE10 15

71: #define LED 7

72:

```

and configured them as follows

defined as

what I had observed as that the GPIO_0 DIRM and OEN were not allowing the GPIO 0 pins to

drive the PMOD so I explicitly set them

What I observed is I was only able to write the lower 8 bits of each of these registers.

### before

code to change **DIRM** and **OEN**

```

u32 pGPIO_0_DIRM = 0xE000A204;

Xil_Out32(pGPIO_0_DIRM, (u32)(iMask));

u32 pGPIO_0_OEN = 0xE000A208;

Xil_Out32(pGPIO_0_OEN, (u32)(iMask));

```

### after

Note that bits 8-15 were ignored.

This is also the case if I try to modify them from the ide memory window. If I write 0xffffffff only the lower 8 bits are modified.

(Both DIRM and OEN)

Why is this?

Setting up PLL for use with FPGA fabric

hawx2020 — Mon, 06 Jan 2025 20:58:15 GMT

Hi,

I'm having trouble setting up the 33MHz PLL clock so that I am able to access it from the FPGA fabric. I've never used a PLL before and I've only ever used the FPGA fabric on the zedboard so I'm not quite sure where to start. If anyone has any advice or an example project, that would be greatly appreciated.

Thanks!

audio passthrough using SPI in PL

Former Member — Sat, 04 Jan 2025 02:26:03 GMT

Hi!

I'm new to FPGA and ZedBoard, and for educational purpose, I'm trying to recive signal from microphone(or LINE_IN) and passthrough it to headphones(or LINE_OUT). Eventually I'm going to create a sound recognition system(frequency detection to be precisie), but for now, I want to properly set up audio codec, and check on headphones if I can hear myself. I found interesting project here: https://www.rtlaudiolab.com/page/4/ (part1-5) that describes how to passtrough audio using SPI communication. I set up everything, just like on this website, but have a problem with SPI driver(which is the codec audio if I understand that correctly), because the data_in are going nowhere. I don't know if that's how it supossed to be, but common sense tell me that it shouldn't be that way. Also, I can generate a bitstream and program zedboard, but i can't hear nothing.

I would be thankful for any advice and help.

PS. Acording to website of the project, i should press BTNC before i could hear anything but that doesn;t help either.

Here are screenshots from the vivado:

Zedboard troubleshooting : Power LED and DONE LED does not turn ON

teem-8121 — Thu, 24 Oct 2024 16:38:53 GMT

The zedboard was working all fine.

But suddenly the Power LED, DONE LED, does not turn ON when 12V adaptor is plugged in with Switch ON, whereas the LD0 to LD7 stays ON in red when the board is powered.

I checked for the voltage across the following Capacitors with a DMM while the Zedboard is powered:
C328, C329 or C330 ( should be 5V)
C334 or C335 ( should be 3.3V)
C351 or C352 ( should be 1.5V)
C365 or C366 ( should be 1.8V)
C356 or C357 ( should be 1V)
I also verified the fuse voltage F5 and the switch SW8
All of these measured as expected. Not sure what could have went wrong.

Could you suggest some more steps to troubleshoot?

Zedboard Gerber Files

OliverMcDonald — Tue, 10 Sep 2024 21:05:34 GMT

Where can I find the Gerber files for the PCB of the Zedboard?

End of Life of Zedboard

OliverMcDonald — Tue, 10 Sep 2024 20:06:31 GMT

Given that the Zedboard is over 10 years old, how much longer does Avnet intend to sell the Zed board?

ZedBoard

OliverMcDonald — Tue, 10 Sep 2024 18:08:07 GMT

I bought a ZedBoard Part number AES-Z7EV-7Z020-G. It was my understanding that support for the board would be located at zedboard.org. However, when I tried going to that site, it appears that the site does not exist anymore. My questions to you are:

How much longer does Avnet plans to manufacture the Zedboard?
When does Avnet intend to re-activate the site zedboard.org?
Are gerber files of the circuit board available?

Issues with Custom Memory Interface

dniemann17 — Tue, 27 Aug 2024 15:19:37 GMT

Hello!

We are currently using a Zedboard to create a custom AXI memory and register interface from a verilog file.

The memory interface is 16K words and uses AXI4 FULL, and the register interface is 32K words and uses AXI Lite

As of writing, we are able to do the following with these interfaces using a CLI:

Read custom register interface
Write to custom register interface
- Confirm data written can be read again
Read custom memory interface

We are having issues trying to write to the custom memory interface.

All that the software CLI does is parse out an address and use Xil_In/Xil_Out to read/write to ZedBoard memory

This feature has been tested extensively on other projects and other sections of memory on the ZedBoard, all of which work perfectly normally

We believe this is a Verilog error and want advice/help with testing and simulating the AXI bus to try and find the issue.

We looked for an AXI bus testing solution, but the posts on the Xilinx website were all out of date and unable to be followed (we run 2023.2 and the guides were written for 2019.2).

Contained below is a list of files associated with a block diagram of our project (I've had to rename them to .txt files to upload).

xilinx_tdpram_1024x36.v ====> Base single memory block file

dig_core_dpram_32.v ====> Top memory file (contains 4 rams)

proto_core_top_regs_ex.v ====> Top register file

pocket_interface_v1_0.v ====> Top reg/mem interface file

pocket_interface_v1_0_S00_AXI.v ====> Register AXI interface file

pocket_interface_v1_0_S01_AXI.v ====> Memory AXI interface file

Currently it seems that pocket_interface_v1_0_S01_AXI.v is the main problem with the temporary write address or "axi_awaddr" being the likely cause, but we can't be fully sure.

Any help with the error or testing methodology would be appreciated.

Regards,

Daniel

community.element14.com/.../xilinx_5F00_tdpram_5F00_1024x36.txt community.element14.com/.../pocket_5F00_interface_5F00_v1_5F00_0.txt community.element14.com/.../dig_5F00_core_5F00_dpram_5F00_32.txt community.element14.com/.../pocket_5F00_interface_5F00_v1_5F00_0_5F00_S00_5F00_AXI.txt community.element14.com/.../pocket_5F00_interface_5F00_v1_5F00_0_5F00_S01_5F00_AXI.txt community.element14.com/.../proto_5F00_core_5F00_top_5F00_regs_5F00_ex.txt

Zedboard compatible with Xilinx HW-FMC-105-DEBUG board ?

tintinxyz — Mon, 08 Jul 2024 05:57:54 GMT

Hi,

Can anyone pls tell me how to check if the zedboard is electrically compatible with HW-FMC-105-DEBUG board ?

Thanks in advance !

Regards.

Viavdo - Zynq7000(Linux - Ubuntu) - PL

angerpro — Wed, 22 May 2024 13:41:04 GMT

Hi guys, I am in a project that I need to boot Linux OS to ARM a9 in Zynq7000(Zedboard). Before my way to design FPGA is Vivado -> .XSA file -> Download XSA file in Vitis -> use Vitis to manage PS and control data path, get result and etc.
Now instead of using Vitis, is there any way that I use Vivado to create block design -> export hardware(include bitstream) .XSA file -> send it to Linux - particularly Ubuntu (inside ARM core a9) -> then use it to implementation PL? and after that I can use directly Linux os to control the peripherals as Leds, Switches, vga??? I saw some tutorials that uses Petalinux, my opinion is that Petalinux is convinient but heaveweight. If I can not use OS like Ubuntu, even simpler Debian, then last choice I will use Petalinux.

Thansk for reading my question. And also my English is not really good, sorry if there are obscure questions.

SD card files formatted

AWM — Mon, 20 May 2024 17:06:36 GMT

Hello,

I was trying to configure the zedboard on linux and i was following https://digilent.com/reference/_media/zedboard_gswel_guide.pdf as a guide. Now, I want to shift on Windows. I was following the steps, It said to format the SD Card, and I formatted SD card. Now, I have to shift it to windows and run it there, I cannot locate SD card files anywhere on internet. Can someone help me resolve this issue, or provide me with the files?

Any help will be appreciated.

Thanks,

AWM

How can the ADAU1761 ZedBoard be configured in SPI mode for audio pass-through?

Adelynul — Wed, 01 May 2024 22:44:41 GMT

Hello everyone for some weeks now i try to pass through the zedboard audio codec (ADAU1761) sound, initially i found a very useful tutorial at www.rtlaudiolab.com/.../ which i followed but without success. My intention and what i have done is implementing the same logic in VHDL, but something it is not working i tested the SystemVerilog code and it worked. I am not really sure what went wrong and if someone could loom over my code or point me into the right direction because i do not know what to do anymore especially that over the internet it seems that is a lack of resources about this topic(I also found the github repository of Microelectronic Systems Design Research Group, but they implement it over I2C which is not what i need.

Here is the WeTransfer link with both archives of systemverilog code and vhdl code that i tried, thank you in advance for reading my post and trying to help https://we.tl/t-4iSOKsY3nF

ZEDBOARD UART-USB connection problem in linux while using matlab

Rohith_Gopakumar — Wed, 03 Apr 2024 15:27:56 GMT

hello i am new to zedboard and am trying to set up the hardware since the past few weeks so any help would be great. i am trying to connect the board to the development computer

TOOL VERSIONS:

matlab version-R2022b

os-Ubuntu 20.04.3 LTS

i have used HDL Coder Support Package for Xilinx Zynq Platform

I keep getting this error and i'm not sure how to resolve it, any and all help would be appreciated thank you

----------------------------------------------------------------------------------------------------------------------------------------------

attempts done:

1)i have tried to setup serial port using s=serialport('dev/ttyACM0',115200); fopen(s) then tried the hardware

2)i have given permissions for dev/ttyACM0 by chmod 666

3)i have used putty to communicate with the zynq board

Implementing Vitis C code with Vivaod Verilog code

CJK15 — Tue, 05 Mar 2024 16:09:20 GMT

I am currently using a PmodAD1 with code in Vitis as an ADC. The code reads the digital value obtained by the Pmod and writes it to the serial monitor. I intend to utilize this value to generate a PWM signal, with the duty cycle adjusting according to the input changes. The Pmod is currently operational, and I can generate a PWM signal in Verilog in separate projects. Modifying the duty cycle in the PWM Verilog code requires regenerating a bitstream and reprogramming the device each time. How can I integrate these components to have the PWM automatically update based on the Pmod's input? I am a student and would appreciate any advice. Thanks

My block design:

My Verilog Code:

Reading mouse over USB OTG port on Zedboard

average_mid — Mon, 04 Mar 2024 06:16:13 GMT

I am looking to develop my own custom IP in Vivado to read mouse input from the USB OTG port on a Zedboard (digilent.com/.../start).

I've scoured the internet for information but they almost all point to using PS/2 Pmods to achieve this. If I can read a flash drive using the OTG port, I should be able to read mouse signals provided I have the necessary USB A to microUSB adaptor. I'm not even sure where to start as computer mouse are HID devices and I don't quite know how a mouse's signal is presented over the OTG port.

Anyone with insight into this is greatly appreciated!

ZedBoard not booting, u-boot file is corrupted

CJK15 — Mon, 19 Feb 2024 19:44:34 GMT

My ZedBoard will not boot from the SD card. It was able to boot in the past, so I know I have the right jumper configurations. I looked at the SD card, and the U-boot is corrupted. I have tried to install a new u-boot file using the out-of-box demo zip file posted on Digilent. It led me here. However, I am still having trouble installing a new U-boot file. Any help would be greatly appreciated.

New zed board is not booting from SD card despite jumper configuration.

fluxinduction — Mon, 29 Jan 2024 18:57:06 GMT

I've been following this guide for initial setup of the zedboard:

GS-AES-Z7EV-7Z020-G-V7-1.pdf (avnet.com)

I cannot get past step 8 of section 5. The zedboard never successfully boots. I do have another SD card, and that doesn't boot either.

I've also been referencing the hardware guide:

ZedBoard_HW_Users_Guide (digilent.com)

What is causing this? This board is brand new, just unwrapped.

Zedboard - writing mcs file to flash - can't make that happen

TorstenS — Mon, 30 Oct 2023 16:46:10 GMT

Hello - I've been trying to get the MCS generated in SDK to be written to the flash on the Zedboard. The installed Flash is an S25FL256S Quad SPI.

The board does boot from the flash with the jumpers J7 thourgh J11 set to '00010'. At least this indicates the FLASH is in working order.

Writing to to the flash:

Generating basic ‘LED on’ PS/PL in Vivado 2018.3 and SDK 2018.3 (runs fine when just uploading bit file into Zynq from the SDK, and launching the .elf file from the SDK)
In SDK generating FSBL and .mcs file (files are generated as ‘Release’)
Setting JP7 through JP11 all to logic ‘0’
In SDK run XILINX->Program Flash

This is the SDK console output I've been getting:

Connected to hw_server @ TCP:127.0.0.1:3121

Available targets and devices:

Target 0 : jsn-DLC10-00001b311f3601

Device 0: jsn-DLC10-00001b311f3601-4ba00477-0

Retrieving Flash info...

Initialization done, programming the memory

===== mrd->addr=0xF800025C, data=0x00000000 =====

BOOT_MODE REG = 0x00000000

Downloading FSBL...

===== mrd->addr=0xF8000110, data=0x00177EA0 =====

READ: ARM_PLL_CFG (0xF8000110) = 0x00177EA0

===== mrd->addr=0xF8000100, data=0x0001A008 =====

READ: ARM_PLL_CTRL (0xF8000100) = 0x0001A008

===== mrd->addr=0xF8000120, data=0x1F000400 =====

READ: ARM_CLK_CTRL (0xF8000120) = 0x1F000400

===== mrd->addr=0xF8000118, data=0x00177EA0 =====

READ: IO_PLL_CFG (0xF8000118) = 0x00177EA0

===== mrd->addr=0xF8000108, data=0x0001A008 =====

READ: IO_PLL_CTRL (0xF8000108) = 0x0001A008

Problem in Initializing Hardware

Flash programming initialization failed.

ERROR: Flash Operation Failed

I've tried writing to the flash from Vivado instead of the SDK - in VIVADO there is a whole family of S25FL256S flashes available. Out of desperation I tried them all - all resulting in the same message as above.

Any support and insight into this problem is greatly appreciated.

Thank you in advance!

Torsten

Repair Zedboard

DDina — Wed, 26 Jul 2023 20:54:40 GMT

Hi,

I contacted you to check if you accept to repair the zedboard FPGAs. From past 1 year and 6 months onwards I am working on zedboard, but this week when I turned on the power supply of the zed board and I didn't do any wrong operations, its not getting turning on, the green LED is not turning on( power status).

I will wait for your answer. Also I have a similar issue with my previous board.

Thank you so much.

regards

ZedBoard Rev f Netlist

darshansm — Thu, 13 Apr 2023 08:50:04 GMT

For Boundary scan, required ODB++ files/ Netlist. Where can we get that??

AES-Z7EV-7Z020-G ZedBoard - Zynq SoC Development Board with FMC LPC/JTAG/UART Interface

Zero — Wed, 16 Nov 2022 08:21:39 GMT

anyone can help me with H.S code and weight of this item

AES-Z7EV-7Z020-G
ZedBoard - Zynq SoC Development Board with FMC LPC/JTAG/UART Interface

Zedboard trying to detect and output voltage

JavierToh — Wed, 12 Oct 2022 05:28:25 GMT

I trying to use the Zedboard to detect a voltage level and output another voltage.

Been trying to find ways to do it but everything seems to be outdated or unable to be used.

I trying to use XADC or PMOD in order to detect a specific voltage from external circuit before outputing another voltage into another circuit